Fix shared local mem mapping issue

CTSRD-CHERI · Apr 27, 2023 · c4837bd · c4837bd
1 parent a8c35d7
commit c4837bd
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Showing 11 changed files with 11 additions and 11 deletions.
diff --git a/apps/TestSuite/A/amoadd_w.S b/apps/TestSuite/A/amoadd_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero

diff --git a/apps/TestSuite/A/amoand_w.S b/apps/TestSuite/A/amoand_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero

diff --git a/apps/TestSuite/A/amomax_w.S b/apps/TestSuite/A/amomax_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero

diff --git a/apps/TestSuite/A/amomaxu_w.S b/apps/TestSuite/A/amomaxu_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero

diff --git a/apps/TestSuite/A/amomin_w.S b/apps/TestSuite/A/amomin_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero

diff --git a/apps/TestSuite/A/amominu_w.S b/apps/TestSuite/A/amominu_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero

diff --git a/apps/TestSuite/A/amoor_w.S b/apps/TestSuite/A/amoor_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero

diff --git a/apps/TestSuite/A/amoswap_w.S b/apps/TestSuite/A/amoswap_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero

diff --git a/apps/TestSuite/A/amoxor_w.S b/apps/TestSuite/A/amoxor_w.S
@@ -20,7 +20,7 @@ RVTEST_CODE_BEGIN
   #define ADDR (\
     1 << (DRAMAddrWidth + DRAMBeatLogBytes) - \
     1 << (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack) - \
-    1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank + 2))
+    1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank + 2))
 
   # Use only a single thread for this test
   csrrw t3, 0xf14, zero

diff --git a/inc/MemoryMap.h b/inc/MemoryMap.h
@@ -19,7 +19,7 @@ NOTE("These stacks appear at the end of DRAM")
 
 NOTE("Sum of sizes of banked SRAMs")
 #define BANKED_SRAMS_SIZE \
-  (1 << (SIMTLogLanes + SIMTLogWordsPerSRAMBank+2))
+  (1 << (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank+2))
 
 NOTE("SIMT local memory is toward the end of DRAM, before the SIMT stacks")
 #define LOCAL_MEM_BASE (DRAM_SIZE - SIMT_STACKS_SIZE - BANKED_SRAMS_SIZE)

diff --git a/src/Main.hs b/src/Main.hs
@@ -310,7 +310,7 @@ makeSIMTMemSubsystem dramResps = mdo
     -- SRAM-related addresses
     simtStacksStart = 2 ^ (DRAMAddrWidth + DRAMBeatLogBytes) -
       2 ^ (SIMTLogLanes + SIMTLogWarps + SIMTLogBytesPerStack)
-    sramSize = 2 ^ (SIMTLogLanes + SIMTLogWordsPerSRAMBank+2)
+    sramSize = 2 ^ (SIMTLogSRAMBanks + SIMTLogWordsPerSRAMBank+2)
     sramBase = simtStacksStart - sramSize
 
     -- Determine if request maps to banked SRAMs