RISC-V ISA ref: Add new functions for DDC/PCC relocation

CTSRD-CHERI · Aug 7, 2023 · 0a0647a · 0a0647a
1 parent b95fe95
commit 0a0647a
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/chap-isaref-riscv.tex b/chap-isaref-riscv.tex
@@ -155,6 +155,7 @@ \subsection*{Functions for reading and writing registers and memory}
 \sailRISCVval{mem\_read\_cap}
 
 \medskip
+\sailRISCVval{ddc\_and\_resulting\_addr}
 \sailRISCVval{get\_cheri\_mode\_cap\_addr}
 \sailRISCVval{handle\_load\_cap\_via\_cap}
 \sailRISCVval{handle\_load\_data\_via\_cap}
@@ -251,6 +252,7 @@ \subsection*{Checking for availability of ISA features}
 \sailRISCVval{haveFExt}
 \sailRISCVval{haveNExt}
 \sailRISCVval{haveSupMode}
+\sailRISCVval{have\_pcc\_relocation}
 
 
 \section{CHERI-RISC-V Instructions}