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RISC-V: Add a note for the reset value of xCCSR.
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bsdjhb committed Aug 4, 2023
1 parent 2874722 commit 37d7178
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4 changes: 4 additions & 0 deletions chap-cheri-riscv.tex
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@@ -456,6 +456,10 @@ \subsubsection{Capability Control and Status Registers (CCSRs)}
\riscvcheriexception{} exception (0).
\end{description}

An implementation compliant with the current version of this
specification sets the \texttt{nr} and \texttt{tc} bits to 1 and all
other bits to 0 at reset.

\subsection{Special Capability Registers (SCRs)}
\label{subsection:cheri-riscv-scrs}

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