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RISC-V: Remove the CSub instruction.
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It was no longer needed after the removal of split register file
support and CHERI LLVM no longer emits it.  It remains in the ISA
quick reference summary table with a stub entry marking the encoding
as a removed instruction.
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bsdjhb committed Jul 12, 2023
1 parent a83e324 commit 5f2f35f
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Showing 7 changed files with 13 additions and 36 deletions.
13 changes: 4 additions & 9 deletions app-isaquick-riscv.tex
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Expand Up @@ -114,13 +114,6 @@ \chapter{CHERI-RISC-V ISA Quick Reference}

\rvcheriisaquick{CFromPtr}

\jwnote{We do not need CSub, since a standard Sub will return the difference between two capabilities.}

\jrtcnote{We do need a separate CSub with a split register file though,
so we define one that should be used even with a merged register file.}

\rvcheriisaquick{CSub}

\rvcheriisaquick{CMove}

%\dcnote{We probably shouldn't have these, because RISC-V doesn't have equivalents for integer registers - or we should define these as working on all registers.}
Expand Down Expand Up @@ -760,10 +753,12 @@ \chapter{CHERI-RISC-V ISA Quick Reference}
\vspace{1em}

{\rvcherienctablefontsize
\def\rvcherireservedfootnotemark{$^\dagger$}
\def\rvcheriremovedfootnotemark{$^\dagger$}
\def\rvcherireservedfootnotemark{$^\ddagger$}
\rvcherienctablesrcsrcdest\\\\
\footnotesize
$^\dagger$Reserved for future use.
$^\dagger$Previously used by a removed instruction.\\
$^\ddagger$Reserved for future use.
}

\subsection*{Stores encoding allocation (rd field)}
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4 changes: 2 additions & 2 deletions app-versions.tex
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Expand Up @@ -567,7 +567,7 @@ \section{Detailed CHERI ISA Version Change History}
\insnnoref{CEQ} instruction checked only that their offsets pointed at the
same location.

A new capability instruction, \insnref{CSUB}, allows the implementation
A new capability instruction, \insnnoref{CSUB}, allows the implementation
of C-language pointer subtraction semantics with the atomicity properties
required for garbage collection.

Expand Down Expand Up @@ -724,7 +724,7 @@ \section{Detailed CHERI ISA Version Change History}
\insnref{CUnseal} instruction, and an explanation added.

Opcodes have now been specified for the \insnref{CSetBoundsExact} and
\insnref{CSub} instructions.
\insnnoref{CSub} instructions.

To improve code generation when constructing a \PCC{}-relative capability as
a jump target, a new \insnnoref{CGetPCCSetOffset} instruction has been
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8 changes: 4 additions & 4 deletions chap-architecture.tex
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Expand Up @@ -1631,9 +1631,9 @@ \section{Capability-Aware Instructions}
These support efficient hybrid code, in which use of integer pointers and
capabilities are intermixed.

\item[Capability pointer comparison and arithmetic]
These instructions provide pointer comparison and
subtraction behavior: \insnref{CSetEqualExact}, \insnref{CSub}, and
\item[Capability pointer comparison]
These instructions provide pointer comparison:
\insnref{CSetEqualExact} and
\insnref{CTestSubset}.

\item[Load or store via a capability]
Expand Down Expand Up @@ -3044,7 +3044,7 @@ \section{Potential Future Changes to the CHERI Architecture}
they have $base=0$ and $length=2^{64}$ for the purposes of the
instructions where this matters, namely \insnref{CGetBase},
\insnref{CGetOffset}, \insnref{CIncOffset},
\insnref{CGetLen} and \insnref{CSub}.
and \insnref{CGetLen}.
However, there is also a desire that \insnref{CSetOffset} should preserve
the values of $T$ and $B$ for debugging purposes, where possible.

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5 changes: 2 additions & 3 deletions chap-cheri-riscv.tex
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Expand Up @@ -1420,11 +1420,10 @@ \subsection{Separate Capability Register File}
obtained by reading the aliased general-purpose integer register.
Note that \insnref{CGetAddr} is currently still defined.

\item A separate \insnref{CSub} instruction to compute the difference
\item A separate \insnnoref{CSub} instruction to compute the difference
between addresses in two capability registers. In a ``merged''
register file this can be computed via the existing \insnnoref{SUB}
instruction on the aliased general-purpose integer registers. Note
that \insnref{CSub} is currently still defined.
instruction on the aliased general-purpose integer registers.

\item Dirty bits were defined in a the per-mode CSR \xccsr{}. This bit
was set anytime a general-purpose capability register was changed.
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1 change: 0 additions & 1 deletion chap-isaref-riscv.tex
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Expand Up @@ -287,7 +287,6 @@ \section{CHERI-RISC-V Instructions}
\input{insn-riscv/csethigh}
\input{insn-riscv/csetoffset}
\input{insn-riscv/cspecialrw}
\input{insn-riscv/csub}
\input{insn-riscv/ctestsubset}
\input{insn-riscv/ctoptr}
\input{insn-riscv/cunseal}
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2 changes: 1 addition & 1 deletion def-riscv-insns.tex
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Expand Up @@ -49,7 +49,7 @@

\rvcherisrcsrcdest[name=CToPtr]{12}{rd}{cs1}{cs2}
\rvcherisrcsrcdest[name=CFromPtr]{13}{cd}{cs1}{rs2}
\rvcherisrcsrcdest[name=CSub]{14}{rd}{cs1}{cs2}
\rvcherisrcsrcdest[name=CSub,noref,tablesuffix=\rvcheriremovedfootnotemark]{14}{rd}{cs1}{cs2}
\rvcherisrcdest[name=CMove]{A}{cd}{cs1}

\rvcherisrcsrcdest[name=CTestSubset]{20}{rd}{cs1}{cs2}
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16 changes: 0 additions & 16 deletions insn-riscv/csub.tex

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