Qualify 32-bit vs 64-bit CHERI-RISC-V maturity.

chap-architecture.tex

@@ -36,8 +36,9 @@ \section{Architectural Instantiations of CHERI Protection}
   implementations, adaptations of our CheriBSD and CheriFreeRTOS operating
   systems, Clang/LLVM/LLD toolchain, GDB debugger, and application suite.
 
-  We expect continuing disruptive modification to this ISA mapping, including
-  reencoding of many key instructions, as it transitions to a more mature
+  We aim to propose 64-bit CHERI-RISC-V as a RISC-V extension with
+  minimal adjustments.  We consider 32-bit CHERI-RISC-V less mature
+  and expect future disruptive modifications as it transitions to a more mature
   status.
 
 \item[Arm Morello] is an experimental instantiation created by Arm

chap-cheri-riscv.tex

@@ -92,7 +92,7 @@ \subsection{Target RISC-V ISA Variants}
 (\texttt{XLEN}=64) base integer instruction
 sets (RV32I, RV64I). \mmnote{Maybe mention that we don't support RV128I,
 because it has not been ratified yet.}
-Our current proposal would support either mode with few differences beyond
+Our current proposal supports either mode with few differences beyond
 capability width, although safe support for both modes in a single processor
 is not specified at this time.
 \pgnnote{This may be understated.  It may also be misinterpreted,
@@ -109,6 +109,14 @@ \subsection{Target RISC-V ISA Variants}
 We also describe extensions to RVS, the supervisor extension defined in the
 privileged portion of the ISA.
 
+We view 64-bit CHERI-RISC-V as a mature specification suitable as a
+starting point for an official RISC-V extension.  However, we feel
+that 32-bit CHERI-RISC-V is less mature.  In particular, the current
+encoding for 64-bit capabilities provides insufficient precision.
+Further research is needed to determine if an alternate encoding,
+perhaps using an alternate scheme for permissions, can provide better
+precision.
+
 \subsection{CHERI-RISC-V is an ISA Design Space}
 
 A key aim in CHERI-RISC-V is to allow experiments to be run comparing various