RISC-V: Remove an OBE note about RV128.

The chapter discusses RV128 in several other places.

chap-cheri-riscv.tex

@@ -83,8 +83,7 @@ \subsection{Target RISC-V ISA Variants}
 
 The RISC-V ISA defines both 32-bit (\texttt{XLEN}=32) and 64-bit
 (\texttt{XLEN}=64) base integer instruction
-sets (RV32I, RV64I). \mmnote{Maybe mention that we don't support RV128I,
-because it has not been ratified yet.}
+sets (RV32I, RV64I).
 Our current proposal supports either mode with few differences beyond
 capability width, although safe support for both modes in a single processor
 is not specified at this time.