Finalize version 9.

- Set date and remove DRAFT suffix. - Add V9 to the version table and reference it in the intro chapter.
CTSRD-CHERI · Aug 7, 2023 · b3430f5 · b3430f5
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diff --git a/app-versions.tex b/app-versions.tex
@@ -176,7 +176,7 @@ \section{CHERI ISA Specification Version Summary}
   We have added a chapter on practical CHERI microarchitecture.
   CHERI ISAv8 is synchronized with Arm Morello.
 
-\item[CHERI ISAv9 / UCAM-CL-TR-XXX - 9.0 - August 2023]
+\item[CHERI ISAv9 / UCAM-CL-TR-XXX - 9.0 - November 2023]
   CHERI-RISC-V has replaced CHERI-MIPS as the primary reference
   platform, and CHERI-MIPS has been removed from the specification.
   CHERI architectures now always use merged register files where

diff --git a/chap-intro.tex b/chap-intro.tex
@@ -986,9 +986,9 @@ \section{Publications}
 Each has had multiple versions reflecting evolution of our approach:
 
 \begin{itemize}
-\item This report, the \citetitleit{UCAM-CL-TR-951}~\cite{UCAM-CL-TR-850, UCAM-CL-TR-864,
+\item This report, the \citetitleit{UCAM-CL-TR-XXX}~\cite{UCAM-CL-TR-850, UCAM-CL-TR-864,
   UCAM-CL-TR-876, UCAM-CL-TR-891, UCAM-CL-TR-907, UCAM-CL-TR-927,
-  UCAM-CL-TR-951},
+  UCAM-CL-TR-951, UCAM-CL-TR-XXX},
   describes the CHERI ISA, both as a high-level, software-facing
   model and the specific mapping into multiple instruction sets.
   Successive versions have introduced improved C-language support, support for

diff --git a/cheri-architecture.tex b/cheri-architecture.tex
@@ -18,7 +18,7 @@
 \begin{document}
 \title{Capability Hardware Enhanced RISC Instructions: \\
   \smallskip CHERI Instruction-Set Architecture \\
-  {\large Version 9 - DRAFT}}
+  {\large Version 9}}
 \author{
   \parbox{\linewidth}{\centering%
     Robert~N.~M.~Watson,
@@ -53,6 +53,7 @@
   \\
   SRI International, University of Cambridge, and Arm Limited
 }
+\date{1st November 2023}
 
 %% CL tech-report format provides its own cover page
 \ifdefined\trformat

diff --git a/cheri-version-table.tex b/cheri-version-table.tex
@@ -36,5 +36,12 @@
   & & MMU-assisted load-side-barrier revocation \\
   & & Richer microarchitectural exploration \\
   & & Synchronized with Arm Morello architecture~\cite{arm-morello} \\
+  2023 & ISAv9~\cite{UCAM-CL-TR-XXX} & CHERI-RISC-V as primary
+  reference platform \\
+  & & CHERI-MIPS removed \\
+  & & Capabilities stored in general-purpose registers \\
+  & & Clear tags for non-montonic modifications \\
+  & & DCC and PCC relocation disabled by default \\
+  & & CHERI-x86-64 instruction descriptions \\
 \bottomrule
 \end{tabular}