RISC-V: Tweak language for privileged mode.

The current version of the privileged mode spec doesn't really refer
to an S extension anymore.  Rather, it talks about supervisor and
machine-level ISAs that serve as a base for that mode that can have
optional extensions.

chap-cheri-riscv.tex

@@ -98,7 +98,8 @@ \subsection{Target RISC-V ISA Variants}
 We specify CHERI as applied to RVG, which consists of the general-purpose
 elements of the RISC-V ISA: integer, multiplication and division,
 atomic, floating-point, and double floating-point instructions.
-We also describe extensions to RVS, the supervisor extension defined in the
+We also describe extensions to the supervisor-level and machine-level ISAs
+defined in the
 privileged portion of the ISA.
 
 We view 64-bit CHERI-RISC-V as a mature specification suitable as a
@@ -542,8 +543,8 @@ \subsection{Special Capability Registers (SCRs)}
 \bottomrule
 \end{tabular}
 \caption{Special Capability Registers (SCRs).
-SCRs 4-7 are available only with the N extension, and 12-15 only with the S
-extension.
+SCRs 4-7 are available only with the N extension, and 12-15 only with
+supervisor mode.
 \textbf{Modes} shows which RISC-V privilege modes are allowed to access the
 registers.
 \textbf{Access} indicates additional restrictions on accessing the registers: