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Catch up on publications
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Six (!) PhD dissertations, three conference/workshop papers, and a
couple techreports.
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49 changes: 49 additions & 0 deletions chap-intro.tex
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published \citetitleit{cornucopia}~\cite{cornucopia}.
This paper describes a full hardware-software implementation of temporal
memory safety for CHERI, including architectural accelerations.

\item In the proceedings of Hardware and Architectural Support for Security
and Privacy (HASP 2020), we published \citetitleit{DBLP:conf/micro/MarkettosBBNMW20}~\cite{DBLP:conf/micro/MarkettosBBNMW20}.
This paper proposes new solutions that can efficiently address the problem
of malicious memory access from pluggable computer peripherals and
microcontrollers embedded within a system-on-chip.

\item In Workshop on Computer Architecture Research with RISC-V (CARRV 2021),
we published \citetitleit{fuchs2021framework}~\cite{fuchs2021framework}.
This paper presents a flexible and extensible bare-metal test suite containing replications of all major transient-execution attacks in RISC-V.

\item In the proceedings of the 31st European Symposium on Programming
(ESOP 2022) we published \citetitleit{DBLP:conf/esop/BauereissCSAESB22}~\cite{DBLP:conf/esop/BauereissCSAESB22}.
In this paper we define the fundamental security property that Morello aims
to provide: reachable capability monotonicity, and prove that the
architecture definition satisfies it. We also published an extended
version as a technical report~\cite{UCAM-CL-TR-959}.
\end{itemize}

We have additionally released several technical reports, including this
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introduction to pure-capability C/C++, variants of the C and C++ programming
languages targeting implementation of all pointers using CHERI architectural
capabilities.

\item The \citetitleit{UCAM-CL-TR-982}~\cite{UCAM-CL-TR-982} lays out the
specific architectural security objectives of the Arm Morello prototype,
as well as areas that fell out of scope for the project.
\end{itemize}

The following technical reports are PhD dissertations that describe both CHERI
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describes the implementation
of C/C++ compilation and linkage using CHERI capabilities for spatial memory
safety~\cite{UCAM-CL-TR-949}.

\item Hongyan Xia's PhD dissertation, \citetitleit{UCAM-CL-TR-955},
describes 64-bit CHERI capabilities along with a real-time OS to evaluate
their effectiveness\cite{UCAM-CL-TR-955}.

\item Lawrence Esswood's PhD dissertation, \citetitleit{UCAM-CL-TR-961},
describes CheriOS, a clean-slate CHERI-specific
operating system and hypervisor~\cite{UCAM-CL-TR-961}.

\item Michael Dodson's PhD dissertation, \citetitleit{UCAM-CL-TR-963},
demostrates the composition of hardware-enforced architectural capabilities
and cryptographic network tokens to implement object capabilities in a
distributed cyber physical system~\cite{UCAM-CL-TR-963}.

\item Brett Gutstein's PhD dissertation, \citetitleit{UCAM-CL-TR-975},
describes a memory-operations framework for reasoning about memory-safety
mitigations, presents a CHERI-aware implemention of Apple’s JavaScriptCore,
and describes the Cornucopia temporal memory safety implementation~\cite{UCAM-CL-TR-975}.

\item Hesham Almatary's PhD dissertation, \citetitleit{UCAM-CL-TR-976},
describes CompartOS, a new lightweight hardware-software compartmentalisation
model building on CHERI to secure mainstream and complex embedded software
systems~\cite{UCAM-CL-TR-976}.

\item Peter Rugg's PhD dissertation, \citetitleit{UCAM-CL-TR-984},
describes the implementation of CHERI on three RISC-V microarchitectures
as well as the refinement of support for temporal memory
safety~\cite{UCAM-CL-TR-984}.
\end{itemize}

As our research proceeded, and prior to our conference and journal articles,
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129 changes: 129 additions & 0 deletions cheri.bib
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number={3},
pages={50-57},
doi={10.1109/MM.2023.3264676}}

@inproceedings{DBLP:conf/micro/MarkettosBBNMW20,
author = {A. Theodore Markettos and
John Baldwin and
Ruslan Bukin and
Peter G. Neumann and
Simon W. Moore and
Robert N. M. Watson},
editor = {Jakub Szefer and
Weidong Shi and
Ruby B. Lee},
title = {Position Paper: Defending Direct Memory Access with {CHERI} Capabilities},
booktitle = {HASP@MICRO 2020: Hardware and Architectural Support for Security and
Privacy, Virtual Event, Greece, 17 October 2020},
pages = {7:1--7:9},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3458903.3458910},
doi = {10.1145/3458903.3458910},
timestamp = {Tue, 26 Oct 2021 15:45:59 +0200},
biburl = {https://dblp.org/rec/conf/micro/MarkettosBBNMW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{fuchs2021framework,
title={Developing a Test Suite for Transient-Execution Attacks on RISC-V and CHERI-RISC-V},
author={Fuchs, Franz A. and Woodruff, Jonathan and Moore, Simon W. and Neumann, Peter G. and Watson, Robert N.M.},
booktitle={Workshop on Computer Architecture Research with RISC-V},
year={2021}
}

@TechReport{UCAM-CL-TR-955,
author = {Xia, Hongyan},
title = {{Capability memory protection for embedded systems}},
year = 2021,
month = feb,
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-955.pdf},
institution = {University of Cambridge, Computer Laboratory},
doi = {10.48456/tr-955},
number = {UCAM-CL-TR-955}
}

@TechReport{UCAM-CL-TR-959,
author = {Bauereiss, Thomas and Campbell, Brian and Sewell, Thomas
and Armstrong, Alasdair and Esswood, Lawrence and Stark,
Ian and Barnes, Graeme and Watson, Robert N. M. and Sewell,
Peter},
title = {{Verified security for the Morello capability-enhanced
prototype Arm architecture}},
year = 2021,
month = sep,
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-959.pdf},
institution = {University of Cambridge, Computer Laboratory},
doi = {10.48456/tr-959},
number = {UCAM-CL-TR-959}
}

@TechReport{UCAM-CL-TR-961,
author = {Esswood, Lawrence G.},
title = {{CheriOS: designing an untrusted single-address-space
capability operating system utilising capability hardware
and a minimal hypervisor}},
year = 2021,
month = sep,
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-961.pdf},
institution = {University of Cambridge, Computer Laboratory},
doi = {10.48456/tr-961},
number = {UCAM-CL-TR-961}
}

@TechReport{UCAM-CL-TR-963,
author = {Dodson, Michael G.},
title = {{Capability-based access control for cyber physical systems}},
year = 2021,
month = oct,
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-963.pdf},
institution = {University of Cambridge, Computer Laboratory},
doi = {10.48456/tr-963},
number = {UCAM-CL-TR-963}
}

@TechReport{UCAM-CL-TR-975,
author = {Gutstein, Brett},
title = {{Memory safety with CHERI capabilities: security analysis,
language interpreters, and heap temporal safety}},
year = 2022,
month = nov,
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-975.pdf},
institution = {University of Cambridge, Computer Laboratory},
doi = {10.48456/tr-975},
number = {UCAM-CL-TR-975}
}

@TechReport{UCAM-CL-TR-976,
author = {Almatary, Hesham},
title = {{CHERI compartmentalisation for embedded systems}},
year = 2022,
month = nov,
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-976.pdf},
institution = {University of Cambridge, Computer Laboratory},
doi = {10.48456/tr-976},
number = {UCAM-CL-TR-976}
}

@TechReport{UCAM-CL-TR-982,
author = {Watson, Robert N. M. and Barnes, Graeme and Clarke, Jessica
and Grisenthwaite, Richard and Sewell, Peter and Moore,
Simon W. and Woodruff, Jonathan},
title = {{Arm Morello Programme: Architectural security goals and
known limitations}},
year = 2023,
month = jul,
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-982.pdf},
institution = {University of Cambridge, Computer Laboratory},
doi = {10.48456/tr-982},
number = {UCAM-CL-TR-982}
}

@TechReport{UCAM-CL-TR-984,
author = {Rugg, Peter David},
title = {{Efficient spatial and temporal safety for microcontrollers
and application-class processors}},
year = 2023,
month = jul,
url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-984.pdf},
institution = {University of Cambridge, Computer Laboratory},
doi = {10.48456/tr-984},
number = {UCAM-CL-TR-984}
}

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