Code

QEMU Morello#149

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arichardson merged 208 commits intodevCTSRD-CHERI/qemu:devfrom qemu-morello-rebasedCTSRD-CHERI/qemu:qemu-morello-rebasedCopy head branch name to clipboardOct 12, 2021

+49,776-14,563

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Commits on Oct 1, 2021

• Add sail parsing script and its output

  

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• Add morello board hardware

  

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• Add morello CPU type

  

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• Add arm trickbox device

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• Add get_capreg_or_special

  

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• Changes to CHERI common code to support AARCH64

  

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• Add a couple cap cursor modification helpers

  

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• Fix otype sign related issues for AARCH64

  

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• [Morello] DDC interposition depends on CCTLR_DDCBO

  

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• Update generate_get_ddc_checked_gpr_plus_offset for Morello

  

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• Add TCG implementations of some capability operations

  

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• Add basic CHERI support to AARCH64

  

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• Add the morello config files

  

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• Add load/store pair and GCx family of instructions to morello

  

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• Add load pair and branch and link instruction to morello.

  

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• Fix sail parser missing instructions

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• Add tcg condition to string function

  

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• Add sync TCG instruction

  

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• Add static tracking of capability decompression

  

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• Give CapRegState a to string helper

  

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• Make Morello specific changes to cheri utils

  

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• Add another cap debug helper

  

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• Lots more TCG helpers and Morello specific changes to setting offset and bounds

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• Use the common tcg for setting merged registers to integers

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• Pay attention to out of bounds exponants for bounds checks

  

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• build/ccseal/copytype TCG for morello

  

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• [Morello] Implement -cheri-debugger-on-unrepresentable

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• Better tracing of changes to registers

  

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• Move some aarch helpers from internal to cpu.h

  

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• Add restricted mode CSRS. PL_ALL redundant.

  

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• General bug fixes for morello instructions

  

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• Fix sign related issues with atomic operations

  

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• Add helpers to get certain fields without decompression

  

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• Allow atomics on Morello

  

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  4a92e3a

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• Add comments and some missing instructions to arm cheri decode

  

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• Add some bit/byte packing functions

  

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• 64-bit memops should never have MO_SIGN

  

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• Too lazy to fix, adding comment

  

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• Add tag set many. Slightly refactor getting / setting multiple tags with atomicity in mind

  

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• Remove some over-zelous asserts for morello

  

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• Fix off by one on bounds check

  

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• Add some missing gpr_reg_modified calls

  

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• Add CHERI MMU bits to morello

  

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• Add exclusives and multi-tag loads/stores to morello

  

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• TCG for bounds checking normal loads and stores

  

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  4d6daa0

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• Implement alignment and morello exceptions

  

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  bcdda49

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• Fix some capability checking logic for atomic operations

  

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• Always bounds check with length at least 1

  

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  961590d

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• Fix DDC exception number on MIPS

  

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• Remove defunct print

  

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  454fb5e

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• Assert too strict on AARCH64

  

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  97899b6

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• Fix usage of GETPC to only be at top level in helpers

  

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  063e199

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• Define a separate aligned capability type

  

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  825af29

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• Add script to annotate instruction traces with source lines

  

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• Improve implementation of sync

  

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• Add userspace logging console command and remove translation cache flushing on mode change

  

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• Add userspace logging to arm

  

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  115eebc

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• Enabled CHERI tags and logging on arm virt board

  

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  cc8a07b

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• Add debug assert for lazy capreg static optimisation

  

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  86c1d2b

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• Add some missing tcg tmp frees

  

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  3959c8c

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• Fix some cursor sync issues

  

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  6fbaaa0

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• Exceptions write to (and decompress) SP

  

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  5aa971a

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• Cheri-fy arm's TPID registers

  

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  05735ca

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• Do CHERI things for DC ZVA

  

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  3777bf8

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• Fix morello board minimum page size

  

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  276ce4c

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• Restore state before CHERI exceptions on morello

  

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  7c58b8a

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• Add a pytest script to run the morello tests

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• Fix out-of-bounds access found by UBSAN

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• Fix TCG temporary leak in gen_cap_get_type_for_copytype

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• Improve output for failed morello tests

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• disas/libvixl: Rename source files in preparation for update

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• Update disas/libvixl to https://github.com/Linaro/vixl/tree/morello

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• [Morello] Forward PSTATE.C64 to the disassembler

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• [Morello] Fix out-of-bounds access when translating RRLEN

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• [Morello] Always use soft-TLB for tag reads/writes

  

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• Cache instructions should bounds check

  

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  1710a81

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• Fix C64 mode change for exception

  

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  e414345

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• Fix morello 2 stage CHERI mmu permission checks

  

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  bca1c5b

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• Implement unprivileged morello loads/stores

  

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  6e0f456

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• Configure morello cpu features

  

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  1ea2a9e

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• [Morello] remove stray debug prints

  

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  a76bcdb

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• [Morello] Allow capability read/write functions CSRs

  

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  959efe2

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• sp is sometimes register 13

  

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• Add missing newline

  

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• Use qemu_printf

  

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  f8217d6

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• Fix double field initialisation

  

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  b4260b0

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• Fix comments and whitespace

  

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  3acf443

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• Add comment for cache maintenance instructions

  

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  547427c

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• [LD/ST]CT should also do sp_alignment checks

  

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• Fix off by one opc1 for CSCR_EL3

  

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• Cannot use set tag at EL0

  

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  a7f3a80

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• Add CCTLR_EL12 to arm

  

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• Dont unseal untagged sentries

  

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• Generate trace for SCTAG

  

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• Check SP alignment for LD|STCT in non C64 mode

  

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  9cbc241

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• Take PC alignment exceptions on AARCH64

  

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  9d8eda5

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• Fix CHERI MMU bits in stage 2 translation

  

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• Fix off by one in number of flags define

  

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• Morello untags sealed capabilities just before branching to them

  

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• Propagate a faulting address to pcc related faults

  

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• Exception return should also clear tag if capability is sealed

  

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• Propagate address for non-bounds faults for PCC and DDC

  

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• TC TCPAC controls whether exceptions are enabled

  

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• Print better register names when taking an exception

  

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• Exception offset depends on executive bit

  

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  dbdbed1

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• Fix tracing EL

  

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  1ccd929

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• Add better games for AARCH64 DBG registers

  

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  31b7939

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• Enable more breakpoints and watchpoints for morello

  

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  4f2704c

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• Do not claim RAS is implemented on morello

  

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  f9f2c1c

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• SPSel is RAZ/WI in restricted mode

  

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  9d2b701

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• Capabilities enabled exceptions need to set pc properly

  

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  700f961

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• Fix ignoring TGE when E2H enabled

  

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  78b15d5

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• capability access SYN should have IL bit in a64

  

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• Remove assert as behaviour is legal

  

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• Make comment accurate

  

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• Capability return without access system registers untags

  

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  e56117e

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• Correct ESR for SP alignment faults

  

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• MSR immediate also needs to respect CHERI SPSEL rules

  

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  196138c

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• Move PC alignment faults to tb_start to fix alignment priority

  

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  a2edffd

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• Fix lots of unallocated morello encodings

  

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• Take MMU protection faults for capability CAS even when not storing

  

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  ee720b8

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• Add DBGCLAIM CSRS to make testhappy

  

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• Probe with correct sizes so watchpoints trigger correctly

  

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  b024587

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• Move some morello specific logic for capability jumps earlier

  

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  35a328c

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• Fix E2H related mistakes in FP enabled

  

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  662c3a6

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• Fix tag setting enabled

  

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  50d7b9f

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• CAP_NO_SEALING is 64bit, not the size of the type field

  

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• Do representability checks for legacy branches

  

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• Only squash mutable permissions for tagged caps

  

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  6e64963

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• Generate correct ESR for MMU faults due to tags

  

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• Add an always trapping version of PAGE_LC_TRAP

  

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• Handle device memory correctly in conjunction with LC bit

  

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• Fix cache maintenance instructions on morello

  

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• CASL should not tag clear when compare fails

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• Representability check post-index for simd structure load/store

  

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  764c928

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• Correctly set WnR bit for capability MMU faults

  

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• Move TLB tag store faults into probe

  

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• Sort fault priority of atomic cap operations

  

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• Force morello to be little endian

  

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• Handle jumping to non-sentry caps properly

  

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• Morello set bounds immediate is exact

  

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• Fix bounds setting on morello to do sign extention at correct point

  

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• Fix access to sysregs requiring access sysreg permission

  

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• Force printf commit for first instruction in a translation block

  

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• Fix cheri bounds check size for multiple loads

  

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• Expose symbol handling callback to arm boot

  

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• Fail Morello tests with a more useful error message when misconfigured

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• Fix incorrect max_size argument in gen_mov_cap_select()

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• Fix datasize in load/store exlusive pair

  

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• CHERI bounds check needed on another cache op

  

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• Fix cheri permission checks for double cap stores

  

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• Add TCG fast cap add for morello

  

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• Respect exp and valid decode in more places in tcg

  

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• Use CAP_CC() instead of hardcoding CC128

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• [Morello] Fix passing an invalid register number in BLR_BR_RET_CHKD

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• Change a few assertions to be debug-only

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• Make get_load_store_base_cap() always_inline

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• Fix passing argument to handle_sys which does not uses 33 different register numbers

  

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• Add PL_NO_SYSREG to special registers

  

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• Reduce diff to upstream by using g_assert_not_reached()

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• Avoid some large whitespace-only diffs to upstream

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• Don't provide the csetflags helper for Morello

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• Reduce clang-format diffs to upstream

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• Drop duplicate call to cheri_tag_init() for morello board

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• Remove old TARGET_CHERI128 config from morello-softmmu.mak

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• Support GDB for Morello

  

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• Revert "Remove assert as behaviour is legal"

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• Rename TARGET_IS_MORELLO to TARGET_MORELLO

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• Fix some comments

  

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• Branch and link bug has been fixed in ASL

  

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• Use typedef not #define

  

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• Add assert in store tags helper

  

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• Dont assume CC128

  

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• Turn logical op into else branch

  

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• Slightly better comment / name for capability swap

  

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• Distinguish between signed and unsigned in tcg_cond_string

  

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• Sensible ordering in list of masks

  

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• Fix PAGE_C_BITS define to actually include all bits

  

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• Use canonical bit inclusion pattern

  

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• ifdef out dead code

  

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• Neaten up defines

  

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• Less crazy line brbreak

  

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• Fix cpu get asid

  

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• Revert type change in mte_check_zva

  

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• Make the mpidr bit a property

  

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• Small whitespace fix

  

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• Inline return one for is_a64 for cheri arm

  

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• Pass PC to cpu_get_asid

  

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• Make some more TCG work for 32-bit

  

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• Remove stale comments

  

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• Simplify some flow control

  

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• Fix type of placeholder for RISCV target_get_gpr_global

  

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• Change asserts for cap_set_(un)sealed for AARCH64

  

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• morello: Diff-reduce tables (and match style for new ones)

  

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• tcg: Diff-reduce GEN_ATOMIC_HELPER

  

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• morello: Fix up clang-format directives

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• Update clang-format config to be closer to upstream code style

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• Rename INSN_ARM_C64 to ARM_DIS_FLAG_C64

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• Reformat translate-a64.c with IndentCaseBlocks: true

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• Simplify cap_is_unsealed()

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• Clean up Morello ifdefs in cap_set_sealed/cap_set_unsealed

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• Add a cap_unseal_reserved_otype() helper

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• Cleanup cap_is_sealed_with_type()

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• Simplify assertions in cap_set_sealed() and cap_set_unsealed()

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• Fix value of CC{64,128}_LAST_NONRESERVED_OTYPE

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• Stop using CAP_LAST_NONRESERVED_OTYPE

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• [cheri-compressed-cap] Replace FIRST/LAST otype with MIN/MAX

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• [cheri-compressed-cap] Assert cap_pesbt_deposit_X arguments are in range

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