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Enumerating manually instead of using generator for SRAM
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@Peter-Herrmann
Peter-Herrmann committed Oct 21, 2023
1 parent e12ad90 commit b50321d
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6 changes: 2 additions & 4 deletions openlane/soc/config.json
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Original file line number Diff line number Diff line change
Expand Up @@ -68,10 +68,8 @@
"EXTRA_GDS_FILES": ["dir::../../openlane/macros/sky130_sram_2kbyte_1rw1r_32x512_8.gds"],
"ROUTING_CORES": 2,
"KLAYOUT_XOR_THREADS": 2,
"FP_IO_UNMATCHED_ERROR":0,
"FP_PDN_MACRO_HOOKS": [
"sram.sram_blocks.* vccd1 vssd1 vccd1 vssd1"
],
"FP_IO_UNMATCHED_ERROR": 0,
"FP_PDN_MACRO_HOOKS": "sram0 vccd1 vssd1 vccd1 vssd1, sram1 vccd1 vssd1 vccd1 vssd1, sram2 vccd1 vssd1 vccd1 vssd1, sram3 vccd1 vssd1 vccd1 vssd1, sram4 vccd1 vssd1 vccd1 vssd1, sram5 vccd1 vssd1 vccd1 vssd1, sram6 vccd1 vssd1 vccd1 vssd1, sram7 vccd1 vssd1 vccd1 vssd1, sram8 vccd1 vssd1 vccd1 vssd1, sram9 vccd1 vssd1 vccd1 vssd1, sram10 vccd1 vssd1 vccd1 vssd1, sram11 vccd1 vssd1 vccd1 vssd1",
"QUIT_ON_LVS_ERROR": 1,
"CLOCK_PERIOD": 25,
"CLOCK_PORT": "clk_i",
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24 changes: 12 additions & 12 deletions openlane/soc/macro.cfg
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@@ -1,13 +1,13 @@
sram.sram_blocks\[0\].sram1 566.9 300 R180
sram.sram_blocks\[1\].sram1 566.9 786.692 MY
sram.sram_blocks\[2\].sram1 566.9 1253.384 R180
sram.sram_blocks\[3\].sram1 566.9 1710.076 MY
sram.sram_blocks\[4\].sram1 566.9 2196.768 R180
sram.sram_blocks\[5\].sram1 566.9 2683.46 MY
sram0 566.9 300 R180
sram1 566.9 786.692 MY
sram2 566.9 1253.384 R180
sram3 566.9 1710.076 MY
sram4 566.9 2196.768 R180
sram5 566.9 2683.46 MY

sram.sram_blocks\[6\].sram1 1550 300 MX
sram.sram_blocks\[7\].sram1 1550 786.692 R0
sram.sram_blocks\[8\].sram1 1550 1253.384 MX
sram.sram_blocks\[9\].sram1 1550 1710.076 R0
sram.sram_blocks\[10\].sram1 1550 2196.768 MX
sram.sram_blocks\[11\].sram1 1550 2683.46 R0
sram6 1550 300 MX
sram7 1550 786.692 R0
sram8 1550 1253.384 MX
sram9 1550 1710.076 R0
sram10 1550 2196.768 MX
sram11 1550 2683.46 R0
240 changes: 216 additions & 24 deletions verilog/rtl/rtl/soc/modules/sram_wrap.sv
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Expand Up @@ -92,30 +92,222 @@ module sram_wrap #(
cs_inst_prev <= cs_inst;
end

genvar j;
generate
for (j = 0; j < SRAM_NUM_BLOCKS; j++ ) begin : sram_blocks
sky130_sram_2kbyte_1rw1r_32x512_8
#(.DELAY(0))
sram1 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[j]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[j]),
.clk1 (clk_i),
.csb1 (~cs_inst[j]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[j])
);
end
endgenerate
sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram0 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[0]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[0]),
.clk1 (clk_i),
.csb1 (~cs_inst[0]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[0])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram1 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[1]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[1]),
.clk1 (clk_i),
.csb1 (~cs_inst[1]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[1])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram2 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[2]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[2]),
.clk1 (clk_i),
.csb1 (~cs_inst[2]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[2])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram3 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[3]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[3]),
.clk1 (clk_i),
.csb1 (~cs_inst[3]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[3])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram4 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[4]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[4]),
.clk1 (clk_i),
.csb1 (~cs_inst[4]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[4])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram5 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[5]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[5]),
.clk1 (clk_i),
.csb1 (~cs_inst[5]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[5])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram6 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[6]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[6]),
.clk1 (clk_i),
.csb1 (~cs_inst[6]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[6])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram7 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[7]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[7]),
.clk1 (clk_i),
.csb1 (~cs_inst[7]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[7])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram8 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[8]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[8]),
.clk1 (clk_i),
.csb1 (~cs_inst[8]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[8])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram9 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[9]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[9]),
.clk1 (clk_i),
.csb1 (~cs_inst[9]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[9])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram10 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[10]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[10]),
.clk1 (clk_i),
.csb1 (~cs_inst[10]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[10])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram11 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[11]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[11]),
.clk1 (clk_i),
.csb1 (~cs_inst[11]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[11])
);


`ifdef VERILATOR
logic [31:0] _unused;
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