Revert "peripheral control register file fix"

This reverts commit 0690fff.
Cal-Poly-RAMP · Nov 6, 2023 · e407fa4 · e407fa4
1 parent a6d4d79
commit e407fa4
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/verilog/rtl/peripherals/Peripheral_Unit/PeriphControlRegFile.sv b/verilog/rtl/peripherals/Peripheral_Unit/PeriphControlRegFile.sv
@@ -905,7 +905,7 @@ module PeriphControlRegFile #(
 	else begin
 	    GNT <= 1'b1;
 	    RVALID <= 1'b1;
-        if (REQ) begin
+	    if (REQ && BE == 4'b1111) begin
             if (ADDR >= STARTING_ADDR) begin
 	            // RVALID <= 1'b1;
                 if (WRITE) begin
@@ -1348,6 +1348,7 @@ module PeriphControlRegFile #(
                                     end
                                 endcase
                             end
+                            default: DOUT <= 0;
                         endcase
                     end
                 end