Interrupt logic improvements

Cal-Poly-RAMP · Nov 6, 2023 · e4ae80a · e4ae80a
1 parent 1b5fbac
commit e4ae80a
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Showing 4 changed files with 9 additions and 3 deletions.
diff --git a/verilog/rtl/include/clam-defs.svh b/verilog/rtl/include/clam-defs.svh
@@ -24,4 +24,6 @@ typedef enum logic {
 `define SOC_NUM_INTER       52
 // `include "Peripheral_Unit_Defs"
 
+`define CARAVEL_INTR_ADDR   32'hF0000000
+
 `endif // CLAM_DEFS_SVH
diff --git a/verilog/rtl/rtl/soc/clam-defs.svh b/verilog/rtl/rtl/soc/clam-defs.svh
@@ -24,4 +24,6 @@ typedef enum logic {
 `define SOC_NUM_INTER       52
 // `include "Peripheral_Unit_Defs"
 
+`define CARAVEL_INTR_ADDR   32'hF0000000
+
 `endif // CLAM_DEFS_SVH
diff --git a/verilog/rtl/rtl/soc/modules/clam-defs.svh b/verilog/rtl/rtl/soc/modules/clam-defs.svh
@@ -25,4 +25,6 @@ typedef enum logic {
 `define SOC_NUM_INTER       52
 // `include "Peripheral_Unit_Defs"
 
+`define CARAVEL_INTR_ADDR   32'hF0000000
+
 `endif // CLAM_DEFS_SVH
diff --git a/verilog/rtl/rtl/soc/soc.sv b/verilog/rtl/rtl/soc/soc.sv
@@ -742,9 +742,9 @@ module soc (
 
     end
 
-    assign caravel_interrupt_o = illegal_access;
-
-
+    always_comb begin: caravel_interrupt_assignment
+        caravel_interrupt_o = ((dmem_addr == `CARAVEL_INTR_ADDR) & dmem_we) ? {dmem_wdata[1:0],1'b0} : {2'b0, illegal_access};
+    end
     ////////////////////////////////
     // Unused Signal Terminations //
     ////////////////////////////////