1.0.11:
#######
- improved real clock rate from max. 100Hz to max. 250Hz by avoiding:
- use of string += in scheduler
- use of event.wait() which shows a delay of approx. 10ms -> thus the limit of 100Hz
Now time.sleep() is used instead
See # for more information.
*** NOTE: a separate project using a slightly different approach shows clock rates of up to 25kHz !!! ***
*** A new separate project with improved transfer rates will be uploaded to GitHub soon. ***
- added current clock frequency at the center of the FPGA chip
- added workaround to avoid showing zero temperature (in reality we show the CPU load which results sometimes in a zero value)
discovered problems:
- set_spi_din_to_zero() takes too much time!
-> if we use Events(): big jitter, big delay (approx. 10ms)
-> if we use Locks(): miss incomming SPI_SCK while inside set_spi_din_to_zero()
-> if we use a queue(): everything is again delayed and not synchronized!
SPI needs its own scheduler, but this again could be problematic,
here again we need an overall Scheduler with TX, RX synched and asynch events simulated in between.