Merge pull request #3 from pratik-prajapati-imgtec/add_build_cmds_in_…

…readme

Add pistachio soc support

Makefile

@@ -638,6 +638,7 @@ libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
 libs-y += drivers/mtd/onenand/
 libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/
 libs-y += drivers/mtd/spi/
+libs-y += drivers/mtd/spi-nand/
 libs-y += drivers/net/
 libs-y += drivers/net/phy/
 libs-y += drivers/pci/
@@ -767,6 +768,23 @@ endif
 endif
 endif
 
+ifeq ($(CONFIG_MIPS),y)
+ifeq ($(CONFIG_SPL),y)
+ifeq ($(CONFIG_TARGET_PISTACHIO_BUB),y)
+ALL-y += u-boot-pistachio-nor.img
+endif
+ifeq ($(CONFIG_TARGET_PISTACHIO_BEETLE),y)
+ALL-y += u-boot-pistachio-nor.img
+endif
+ifeq ($(CONFIG_TARGET_PISTACHIO_MARDUK),y)
+ALL-y += u-boot-pistachio-nor.img
+endif
+ifeq ($(CONFIG_TARGET_PISTACHIO_CONCERTO),y)
+ALL-y += u-boot-pistachio-nor.img
+endif
+endif
+endif
+
 # Add optional build target if defined in board/cpu/soc headers
 ifneq ($(CONFIG_BUILD_TARGET),)
 ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
@@ -897,6 +915,12 @@ u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
 u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
 	$(call if_changed,mkimage)
 
+u-boot-spl-dtb.bin: spl/u-boot-spl.bin dts/dt.dtb FORCE
+	$(call if_changed,cat)
+
+u-boot-spl-pistachio.bimg: u-boot-spl-dtb.bin FORCE
+	tools/bimgtool $< $@ $(CONFIG_SYS_GRAM_BASE)
+
 MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
 
 u-boot-dtb.img: u-boot-dtb.bin FORCE
@@ -1005,6 +1029,13 @@ u-boot-nand.gph: u-boot.bin FORCE
 	$(call if_changed,mkimage)
 	@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
 
+DEC_UBOOT_OFF:=$(shell $(PERL) -e 'print hex("$(CONFIG_SYS_SPI_U_BOOT_OFFS)");')
+# 512KB of the flash reserved for SPL and 1MB for u-boot payload
+u-boot-pistachio-nor.img: u-boot-dtb.img u-boot-spl-pistachio.bimg FORCE
+	@dd if=/dev/zero of=$@ bs=4K count=384 conv=notrunc
+	@dd if=u-boot-spl-pistachio.bimg of=$@ bs=4K count=128 conv=notrunc
+	@dd if=u-boot-dtb.img of=$@ bs=4K count=256 seek=128 conv=notrunc
+
 # x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
 # reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
 # the middle.

README

@@ -3092,6 +3092,15 @@ CBFS (Coreboot Filesystem) support
 		memories can be connected with a given cs line.
 		Currently Xilinx Zynq qspi supports these type of connections.
 
+		CONFIG_SPI_FLASH_MTD		spi-flash MTD layer
+
+		Define this option to use mtd support for spi flash layer, this
+		adapter is for translating mtd_read/mtd_write commands into
+		spi_flash_read/spi_flash_write commands. It is not intended to
+		use it within sf_cmd or the SPI flash subsystem. Such an adapter
+		is needed for subsystems like UBI which can only operate on top
+		of the MTD layer.
+
 - SystemACE Support:
 		CONFIG_SYSTEMACE
 

README.md

@@ -0,0 +1,29 @@
+# Using u-boot on Creator (Ci40) Marduk platform
+
+### How to build/cross-compile for Ci40:
+
+	$ export CROSS_COMPILE=/path/to/mips-toolchain/mips-toolchain-prefix
+	$ make pistachio_marduk_defconfig
+	$ make
+
+This will generate u-boot-pistachio-nor.img
+
+Note: Using OpenWrt's toolchain toolchain-mipsel_mips32_gcc-5.2.0_musl-1.1.11 will require [this patch](http://lists.denx.de/pipermail/u-boot/2015-July/217911.html) to be applied.
+
+### How to flash on Ci40:
+
+1. [Load OpenWrt](https://github.com/IMGCreator/openwrt/blob/master-pistachio/README.md)
+
+2. Erase and write u-boot image on bootloader partition of Ci40
+
+		$ flashcp -v u-boot-pistachio-nor.img /dev/mtd0
+
+	Note: flashcp needs to be manually selected in OpneWrt menuconfig
+
+		Base system -> busybox -> Cutomize busybox options -> Miscellaneous Utilities -> flashcp
+
+3. Reboot
+
+		$ reboot
+
+_Please be aware that you may brick the board if you flashed a wrong bootloader. Only way to re-cover back the board is to use Dedi-prog SF100 programmer to flash the pre-built bootloader again._

arch/Kconfig

@@ -48,6 +48,7 @@ config MIPS
 	select HAVE_PRIVATE_LIBGCC
 	select HAVE_GENERIC_BOARD
 	select SYS_GENERIC_BOARD
+	select SUPPORT_OF_CONTROL
 
 config NDS32
 	bool "NDS32 architecture"

arch/mips/Kconfig

@@ -11,6 +11,16 @@ config SYS_CPU
 config USE_PRIVATE_LIBGCC
 	default y
 
+config MACH_PISTACHIO
+	bool
+        select SUPPORTS_LITTLE_ENDIAN
+        select SUPPORTS_CPU_MIPS32_R1
+        select SUPPORTS_CPU_MIPS32_R2
+        select DM
+        select DM_SERIAL
+        select SUPPORT_SPL
+        select SPL_DM
+
 choice
 	prompt "Target select"
 	optional
@@ -54,11 +64,27 @@ config TARGET_PB1X00
 	select SUPPORTS_CPU_MIPS32_R2
 	select SYS_MIPS_CACHE_INIT_RAM_LOAD
 
+config TARGET_PISTACHIO_BUB
+	bool "Support Pistachio bring up board"
+	select MACH_PISTACHIO
+
+config TARGET_PISTACHIO_MARDUK
+	bool "Support Pistachio Marduk"
+	select MACH_PISTACHIO
+
+config TARGET_PISTACHIO_BEETLE
+	bool "Support Pistachio Beetle"
+	select MACH_PISTACHIO
+
+config TARGET_PISTACHIO_CONCERTO
+	bool "Support Pistachio Concerto"
+	select MACH_PISTACHIO
 
 endchoice
 
 source "board/dbau1x00/Kconfig"
 source "board/imgtec/malta/Kconfig"
+source "board/imgtec/pistachio_bub/Kconfig"
 source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"

arch/mips/Makefile

@@ -2,9 +2,13 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-head-y := arch/mips/cpu/start.o
+ifneq ($(CONFIG_SPL_START_S_PATH),)
+head-y				:= $(CONFIG_SPL_START_S_PATH:"%"=%)/start.o
+else
+head-y				:= arch/mips/cpu/start.o
+endif
 
-libs-y += arch/mips/cpu/
-libs-y += arch/mips/lib/
+libs-y				+= arch/mips/cpu/
+libs-y				+= arch/mips/lib/
 
-libs-$(CONFIG_SOC_AU1X00) += arch/mips/mach-au1x00/
+libs-$(CONFIG_SOC_AU1X00)	+= arch/mips/mach-au1x00/

arch/mips/cpu/Makefile

@@ -2,8 +2,9 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-extra-y	= start.o
+extra-y	:= start.o
 
-obj-y += time.o
-obj-y += interrupts.o
-obj-y += cpu.o
+obj-y	+= cpu.o
+obj-y	+= interrupts.o
+obj-y	+= mmu.o
+obj-y	+= time.o

arch/mips/cpu/mmu.c

@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2015 Imagination Technologies
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/mipsregs.h>
+#include <asm/mmu.h>
+
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+
+#include <common.h>
+
+#define MIN_PAGE_SIZE SZ_4K
+
+static int add_wired_tlb_entry(u32 entrylo0, u32 entrylo1,
+			       u32 entryhi, u32 pgsize)
+{
+	u32 tlbindex;
+
+	tlbindex = read_c0_wired();
+	if (tlbindex >= get_tlb_size() || tlbindex >= C0_WIRED_MASK) {
+		return -1;
+	}
+	write_c0_wired(tlbindex + 1);
+	write_c0_index(tlbindex);
+	write_c0_pagemask(((pgsize / MIN_PAGE_SIZE) - 1) << C0_PAGEMASK_SHIFT);
+	write_c0_entryhi(entryhi);
+	write_c0_entrylo0(entrylo0);
+	write_c0_entrylo1(entrylo1);
+	mtc0_tlbw_hazard();
+	tlb_write_indexed();
+	tlbw_use_hazard();
+
+	return 0;
+}
+
+static u32 pick_pagesize(u32 start, u32 len)
+{
+	u32 pgsize, max_pgsize;
+
+	max_pgsize = get_max_pagesize();
+	for (pgsize = max_pgsize;
+	     pgsize >= MIN_PAGE_SIZE;
+	     pgsize = pgsize / 4) {
+		/*
+		 * Each TLB entry maps a pair of virtual pages.  To avoid
+		 * aliasing, pick the largest page size that is at most
+		 * half the size of the region we're trying to map.
+		 */
+		if (IS_ALIGNED(start, 2 * pgsize) && (2 * pgsize <= len))
+			break;
+	}
+
+	return pgsize;
+}
+
+/*
+ * Identity map the memory from [start,start+len] in the TLB using the
+ * largest suitable page size so as to conserve TLB entries.
+ */
+int identity_map(u32 start, size_t len, u32 coherency)
+{
+	u32 pgsize, pfn, entryhi, entrylo0, entrylo1;
+
+	coherency &= C0_ENTRYLO_COHERENCY_MASK;
+	while (len > 0) {
+		pgsize = pick_pagesize(start, len);
+		entryhi = start;
+		pfn = start >> 12;
+		entrylo0 = (pfn << C0_ENTRYLO_PFN_SHIFT) | coherency |
+			C0_ENTRYLO_D | C0_ENTRYLO_V | C0_ENTRYLO_G;
+		start += pgsize;
+		len -= min(len, pgsize);
+		if (len >= pgsize) {
+			pfn = start >> 12;
+			entrylo1 = (pfn << C0_ENTRYLO_PFN_SHIFT) |
+				coherency | C0_ENTRYLO_D | C0_ENTRYLO_V |
+				C0_ENTRYLO_G;
+			start += pgsize;
+			len -= min(len, pgsize);
+		} else {
+			entrylo1 = 0;
+		}
+		if (add_wired_tlb_entry(entrylo0, entrylo1, entryhi, pgsize))
+			return -1;
+	}
+
+	return 0;
+}

arch/mips/cpu/start.S

@@ -16,10 +16,15 @@
 #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 #ifndef CONFIG_SYS_INIT_SP_ADDR
 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + \
 				CONFIG_SYS_INIT_SP_OFFSET)
 #endif
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SRAM_BASE + \
+				CONFIG_SYS_SRAM_SIZE)
+#endif
 
 #ifdef CONFIG_32BIT
 # define MIPS_RELOC	3
@@ -162,6 +167,23 @@ reset:
 	mtc0	t0, CP0_CONFIG
 #endif
 
+#ifdef CONFIG_SPL_BUILD
+
+	/* Initialize bss */
+	la	t0, __bss_start
+	move	k0, t0
+	sw	zero, (t0)
+	la	t1, __bss_end - 4
+	blt	t1, t0, stack
+	nop
+clear_bss:
+	addiu	t0, 4
+	sw	zero, (t0)
+	bne	t0, t1, clear_bss
+	nop
+#endif
+
+stack:
 	/* Set up temporary stack */
 	PTR_LI	t0, -16
 	PTR_LI	t1, CONFIG_SYS_INIT_SP_ADDR
@@ -188,10 +210,19 @@ reset:
 	sw	sp, 0(t0)
 #endif
 
+#ifdef CONFIG_IGNORE_BOOT_FLAG
+	move	a0, zero
+#endif
+
 	PTR_LA	t9, board_init_f
 	jr	t9
 	 move	ra, zero
 
+/* Hang for debugging purposes */
+loop:	nop
+	b	loop
+	nop
+
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *

arch/mips/cpu/u-boot.lds

@@ -19,10 +19,12 @@ SECTIONS
 
 	. = ALIGN(4);
 	.text : {
+		__text_start = .;
 		*(.text*)
+		. = ALIGN(8192);
+		__text_end = .;
 	}
 
-	. = ALIGN(4);
 	.rodata : {
 		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
 	}

arch/mips/dts/Makefile

@@ -0,0 +1,12 @@
+dtb-$(CONFIG_MACH_PISTACHIO) += pistachio_bub.dtb pistachio_marduk.dtb pistachio_beetle_mbub.dtb pistachio_concerto_mbub.dtb
+
+targets += $(dtb-y)
+
+# Add any required device tree compiler flags here
+DTC_FLAGS +=
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb

arch/mips/dts/include/dt-bindings

@@ -0,0 +1 @@
+../../../../include/dt-bindings