deploy: b20d803

doc/fpga.html

@@ -285,7 +285,7 @@ <h2>Store package<a class="headerlink" href="#store-package" title="Link to this
 </pre></div>
 </div>
 <p>The output timing is exemplified below.</p>
-<img alt="../_images/wavedrom-e8f762e0-cf4a-46f8-b61f-aeda584738a0.svg" src="../_images/wavedrom-e8f762e0-cf4a-46f8-b61f-aeda584738a0.svg" /><p>During reset, the initial value is set at the output, 1 in this example.
+<img alt="../_images/wavedrom-a95fa812-a0a6-4f25-8a70-157e9558549f.svg" src="../_images/wavedrom-a95fa812-a0a6-4f25-8a70-157e9558549f.svg" /><p>During reset, the initial value is set at the output, 1 in this example.
 When the value is written, via <code class="docutils literal notranslate"><span class="pre">var_in</span></code>, the AXI interface, or via the
 Synchronizer, <code class="docutils literal notranslate"><span class="pre">value</span></code> is updated and <code class="docutils literal notranslate"><span class="pre">updated</span></code> is flagged for one
 clock cycle.  The flag is set at every write, not only when the data
@@ -321,7 +321,7 @@ <h2>Store package<a class="headerlink" href="#store-package" title="Link to this
 </pre></div>
 </div>
 <p>When <code class="docutils literal notranslate"><span class="pre">we</span></code> is high, the <code class="docutils literal notranslate"><span class="pre">value</span></code> is written to the store.</p>
-<img alt="../_images/wavedrom-29d908ce-0c44-414f-8383-a4d718bd0d3d.svg" src="../_images/wavedrom-29d908ce-0c44-414f-8383-a4d718bd0d3d.svg" /><p>In this example, the variable is set to 1 in the second cycle.  Consider
+<img alt="../_images/wavedrom-1361f57e-ac7c-4e7e-b5f0-64f5e7118943.svg" src="../_images/wavedrom-1361f57e-ac7c-4e7e-b5f0-64f5e7118943.svg" /><p>In this example, the variable is set to 1 in the second cycle.  Consider
 the case that a microcontroller and the FPGA synchronize a store.  If a
 variable should be read-only for the microcontroller, <code class="docutils literal notranslate"><span class="pre">we</span></code> can be tied
 high by the FPGA, such that the FPGA updates the variable constantly.  In
@@ -439,7 +439,7 @@ <h2>Protocol<a class="headerlink" href="#protocol" title="Link to this heading">
 </dd>
 </dl>
 <p>Passing messages follows this scheme, which is resembles the AXI4-Stream Protocol:</p>
-<img alt="../_images/wavedrom-3ba58a2b-417f-4ef4-99b2-bd19192f6b1a.svg" src="../_images/wavedrom-3ba58a2b-417f-4ef4-99b2-bd19192f6b1a.svg" /><p><code class="docutils literal notranslate"><span class="pre">data</span></code> is accepted when <code class="docutils literal notranslate"><span class="pre">valid</span></code> and <code class="docutils literal notranslate"><span class="pre">accept</span></code> are high at the same
+<img alt="../_images/wavedrom-877230f9-3a44-46d4-994d-fe1830acb0d7.svg" src="../_images/wavedrom-877230f9-3a44-46d4-994d-fe1830acb0d7.svg" /><p><code class="docutils literal notranslate"><span class="pre">data</span></code> is accepted when <code class="docutils literal notranslate"><span class="pre">valid</span></code> and <code class="docutils literal notranslate"><span class="pre">accept</span></code> are high at the same
 clock edge.  In the example above, this happens at edge 2, 3, 6, 9, and 10.
 There is no order or dependency in <code class="docutils literal notranslate"><span class="pre">valid</span></code> and <code class="docutils literal notranslate"><span class="pre">accept</span></code>; both can be
 high while other is not, indicating ‘there is data’, or ‘the data can be
@@ -765,7 +765,7 @@ <h3>libstored_droptail<a class="headerlink" href="#libstored-droptail" title="Li
 </pre></div>
 </div>
 <p>Example that drops a tail of length 1:</p>
-<img alt="../_images/wavedrom-410bdad7-fa4e-49cd-8458-e42e85d35caa.svg" src="../_images/wavedrom-410bdad7-fa4e-49cd-8458-e42e85d35caa.svg" /><p>Note that the precise latency from <code class="docutils literal notranslate"><span class="pre">data_in</span></code> to <code class="docutils literal notranslate"><span class="pre">data_out</span></code> is
+<img alt="../_images/wavedrom-0c1bcf2d-c7c1-44ae-8b71-9c5f07c87563.svg" src="../_images/wavedrom-0c1bcf2d-c7c1-44ae-8b71-9c5f07c87563.svg" /><p>Note that the precise latency from <code class="docutils literal notranslate"><span class="pre">data_in</span></code> to <code class="docutils literal notranslate"><span class="pre">data_out</span></code> is
 unspecified.</p>
 <dl class="simple">
 <dt>FIFO_DEPTH<span class="classifier">natural := 0</span></dt><dd><p>Minimum FIFO depth. Set to 0 to allow pass-through.</p>
@@ -847,8 +847,8 @@ <h3>libstored_fifo<a class="headerlink" href="#libstored-fifo" title="Link to th
 </pre></div>
 </div>
 <p>Example to drop and commit pushed data:</p>
-<img alt="../_images/wavedrom-6bdf1183-6e9e-4b8c-be56-5bb05508491b.svg" src="../_images/wavedrom-6bdf1183-6e9e-4b8c-be56-5bb05508491b.svg" /><p>Example to drop and commit popped data having a FIFO size of 4:</p>
-<img alt="../_images/wavedrom-d7c74d97-d237-4a6a-9ef1-01ba4345b930.svg" src="../_images/wavedrom-d7c74d97-d237-4a6a-9ef1-01ba4345b930.svg" /><dl class="simple">
+<img alt="../_images/wavedrom-3bbbe8a2-7f8c-42b8-b29b-31928a769370.svg" src="../_images/wavedrom-3bbbe8a2-7f8c-42b8-b29b-31928a769370.svg" /><p>Example to drop and commit popped data having a FIFO size of 4:</p>
+<img alt="../_images/wavedrom-fe7b3b1f-8641-482d-b5c8-847bb0a5c65d.svg" src="../_images/wavedrom-fe7b3b1f-8641-482d-b5c8-847bb0a5c65d.svg" /><dl class="simple">
 <dt>WIDTH<span class="classifier">positive</span></dt><dd><p>Data width.</p>
 </dd>
 <dt>DEPTH<span class="classifier">natural := 1</span></dt><dd><p>Minimum FIFO depth.</p>