zybo: fix PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY error in Vivado. #25
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
The original ZYBO files had negative DQS values and this caused errors in Vivado. This is hardware errata as noted on Digilent site https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual and Xilinx Answer Record 53039
|
this is to fix the Vivado errors about PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY. By setting the values to 0.0, the designs passes Vivado with no errors and still works on the board. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
The original ZYBO files had negative DQS values and this caused errors in Vivado. This is hardware errata as noted on Digilent site https://reference.digilentinc.com/reference/programmable-logic/zybo-z7/reference-manual and Xilinx Answer Record 53039