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Added board files for the NetFPGA 1G CML #33

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Added board files for the NetFPGA 1G CML #33

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7933541
Adding the NetFPGA-1G-CML board files.
Jun 27, 2018
5b00e3d
Adding USB UART PMOD.
Jul 17, 2018
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383 changes: 383 additions & 0 deletions new/board_files/netfpga-1g-cml/F.0/board.xml
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<board schema_version="2.0" vendor="digilentinc.com" name="netfpga-1g-cml" display_name="NetFPGA 1G-CML" url="www.store.digilentinc.com/netfpga-1g-cml-kintex-7-fpga-development-board" preset_file="preset.xml">
<images>
<image name="netfpga-1g-cml.png" display_name="NETFPGA BOARD" sub_type="board">
<description>NetFPGA 1G CML Board File Image</description>
</image>
</images>

<file_version>0.1</file_version>
<compatible_board_revisions>
<revision id="0">F.0</revision>
</compatible_board_revisions>
<description>NetFPGA 1G-CML Development Board</description>
<components>
<component name="part0" display_name="NetFPGA 1G-CML Platform" type="fpga" part_name="xc7k325tffg676-1" pin_map_file="part0_pins.xml" vendor="xilinx">
<interfaces>
<interface mode="slave" name="sys_diff_clock" type="xilinx.com:interface:diff_clock_rtl:1.0" of_component="sys_diff_clock" preset_proc="sys_diff_clock_preset">
<parameters>
<parameter name="frequency" value="200000000"/>
</parameters>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="CLK_P" physical_port="system_clk_p" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="system_clk_p"/>
</pin_maps>
</port_map>
<port_map logical_port="CLK_N" physical_port="system_clk_n" dir="in">
<pin_map port_index="0" component_pin="system_clk_n"/>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="led_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="led_4bits" preset_proc="led_4bits_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_O" physical_port="led" dir="out" left="3" right="0" >
<pin_maps>
<pin_map port_index="0" component_pin="led_0"/>
<pin_map port_index="1" component_pin="led_1"/>
<pin_map port_index="2" component_pin="led_2"/>
<pin_map port_index="3" component_pin="led_3"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="push_button_4bits" type="xilinx.com:interface:gpio_rtl:1.0" of_component="push_button_4bits" preset_proc="push_button_4bits_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_gpio" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="TRI_I" physical_port="btn" dir="in" left="3" right="0" >
<pin_maps>
<pin_map port_index="0" component_pin="btn_0"/>
<pin_map port_index="1" component_pin="btn_1"/>
<pin_map port_index="2" component_pin="btn_2"/>
<pin_map port_index="3" component_pin="btn_3"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
</preferred_ips>
</interface>
<interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
<parameters>
<parameter name="rst_polarity" value="0"/>
</parameters>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="RST" physical_port="reset" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="reset"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<interface mode="master" name="pmod_usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="pmod_usb_uart">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="RxD" physical_port="pmod_usb_uart_if_rx" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="pmod_usb_uart_if_rx"/>
</pin_maps>
</port_map>
<port_map logical_port="TxD" physical_port="pmod_usb_uart_if_tx" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="pmod_usb_uart_if_tx"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<!-- MDC/MDIO shared amongst PHY chips -->
<!-- Make sure this is assigned to ONE of the phy_onboard_# MAC definitions -->
<interface mode="master" name="mdio" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard_1">
<port_maps>
<port_map logical_port="MDIO_I" physical_port="mdio" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="mdio" />
</pin_maps>
</port_map>
<port_map logical_port="MDIO_O" physical_port="mdio" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="mdio" />
</pin_maps>
</port_map>
<port_map logical_port="MDIO_T" physical_port="mdio" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="mdio" />
</pin_maps>
</port_map>
<port_map logical_port="MDC" physical_port="mdc" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="mdc" />
</pin_maps>
</port_map>
</port_maps>
</interface>
<!-- PHY 1 -->
<interface mode="master" name="rgmii_1" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard_1">
<port_maps>
<port_map logical_port="RD" physical_port="rgmii_rxd_1" dir="in" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rxd_1_0"/>
<pin_map port_index="1" component_pin="rgmii_rxd_1_1"/>
<pin_map port_index="2" component_pin="rgmii_rxd_1_2"/>
<pin_map port_index="3" component_pin="rgmii_rxd_1_3"/>
</pin_maps>
</port_map>
<port_map logical_port="TD" physical_port="rgmii_txd_1" dir="out" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_txd_1_0"/>
<pin_map port_index="1" component_pin="rgmii_txd_1_1"/>
<pin_map port_index="2" component_pin="rgmii_txd_1_2"/>
<pin_map port_index="3" component_pin="rgmii_txd_1_3"/>
</pin_maps>
</port_map>
<port_map logical_port="RX_CTL" physical_port="rgmii_rx_ctl_1" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rx_ctl_1"/>
</pin_maps>
</port_map>
<port_map logical_port="TX_CTL" physical_port="rgmii_tx_ctl_1" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_tx_ctl_1"/>
</pin_maps>
</port_map>
<port_map logical_port="RXC" physical_port="rgmii_rxc_1" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rxc_1"/>
</pin_maps>
</port_map>
<port_map logical_port="TXC" physical_port="rgmii_txc_1" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_txc_1"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<!-- PHY 2 -->
<interface mode="master" name="rgmii_2" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard_2">
<port_maps>
<port_map logical_port="RD" physical_port="rgmii_rxd_2" dir="in" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rxd_2_0"/>
<pin_map port_index="1" component_pin="rgmii_rxd_2_1"/>
<pin_map port_index="2" component_pin="rgmii_rxd_2_2"/>
<pin_map port_index="3" component_pin="rgmii_rxd_2_3"/>
</pin_maps>
</port_map>
<port_map logical_port="TD" physical_port="rgmii_txd_2" dir="out" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_txd_2_0"/>
<pin_map port_index="1" component_pin="rgmii_txd_2_1"/>
<pin_map port_index="2" component_pin="rgmii_txd_2_2"/>
<pin_map port_index="3" component_pin="rgmii_txd_2_3"/>
</pin_maps>
</port_map>
<port_map logical_port="RX_CTL" physical_port="rgmii_rx_ctl_2" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rx_ctl_2"/>
</pin_maps>
</port_map>
<port_map logical_port="TX_CTL" physical_port="rgmii_tx_ctl_2" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_tx_ctl_2"/>
</pin_maps>
</port_map>
<port_map logical_port="RXC" physical_port="rgmii_rxc_2" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rxc_2"/>
</pin_maps>
</port_map>
<port_map logical_port="TXC" physical_port="rgmii_txc_2" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_txc_2"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<!-- PHY 3 -->
<interface mode="master" name="rgmii_3" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard_3">
<port_maps>
<port_map logical_port="RD" physical_port="rgmii_rxd_3" dir="in" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rxd_3_0"/>
<pin_map port_index="1" component_pin="rgmii_rxd_3_1"/>
<pin_map port_index="2" component_pin="rgmii_rxd_3_2"/>
<pin_map port_index="3" component_pin="rgmii_rxd_3_3"/>
</pin_maps>
</port_map>
<port_map logical_port="TD" physical_port="rgmii_txd_3" dir="out" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_txd_3_0"/>
<pin_map port_index="1" component_pin="rgmii_txd_3_1"/>
<pin_map port_index="2" component_pin="rgmii_txd_3_2"/>
<pin_map port_index="3" component_pin="rgmii_txd_3_3"/>
</pin_maps>
</port_map>
<port_map logical_port="RX_CTL" physical_port="rgmii_rx_ctl_3" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rx_ctl_3"/>
</pin_maps>
</port_map>
<port_map logical_port="TX_CTL" physical_port="rgmii_tx_ctl_3" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_tx_ctl_3"/>
</pin_maps>
</port_map>
<port_map logical_port="RXC" physical_port="rgmii_rxc_3" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rxc_3"/>
</pin_maps>
</port_map>
<port_map logical_port="TXC" physical_port="rgmii_txc_3" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_txc_3"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
<!-- PHY 4 -->
<interface mode="master" name="rgmii_4" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard_4">
<port_maps>
<port_map logical_port="RD" physical_port="rgmii_rxd_4" dir="in" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rxd_4_0"/>
<pin_map port_index="1" component_pin="rgmii_rxd_4_1"/>
<pin_map port_index="2" component_pin="rgmii_rxd_4_2"/>
<pin_map port_index="3" component_pin="rgmii_rxd_4_3"/>
</pin_maps>
</port_map>
<port_map logical_port="TD" physical_port="rgmii_txd_4" dir="out" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_txd_4_0"/>
<pin_map port_index="1" component_pin="rgmii_txd_4_1"/>
<pin_map port_index="2" component_pin="rgmii_txd_4_2"/>
<pin_map port_index="3" component_pin="rgmii_txd_4_3"/>
</pin_maps>
</port_map>
<port_map logical_port="RX_CTL" physical_port="rgmii_rx_ctl_4" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rx_ctl_4"/>
</pin_maps>
</port_map>
<port_map logical_port="TX_CTL" physical_port="rgmii_tx_ctl_4" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_tx_ctl_4"/>
</pin_maps>
</port_map>
<port_map logical_port="RXC" physical_port="rgmii_rxc_4" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_rxc_4"/>
</pin_maps>
</port_map>
<port_map logical_port="TXC" physical_port="rgmii_txc_4" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="rgmii_txc_4"/>
</pin_maps>
</port_map>
</port_maps>
</interface>
</interfaces>
</component>
<component name="sys_diff_clock" display_name="System Differential Clock" type="chip" sub_type="system_clock" major_group="Clock Sources">
<description>3.3V low-jitter 200 MHz differential output oscillator</description>
</component>
<component name="led_4bits" display_name="4 LEDs" type="chip" sub_type="led" major_group="GPIO">
<description>LEDs 3 to 0</description>
</component>
<component name="push_button_4bits" display_name="4 Push Buttons" type="chip" sub_type="push_button" major_group="GPIO">
<description>Push Buttons 3 to 0</description>
</component>
<component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
<description>512 MB on-board DDR3</description>
</component>
<component name="reset" display_name="Reset Button" type="chip" sub_type="reset" major_group="Reset">
<description>System Reset Button</description>
</component>
<component name="pmod_usb_uart" display_name="PMOD USB-UART" type="chip" sub_type="uart" major_group="UART">
<description>PMOD USB UART on PMOD connector JB top row</description>
</component>
<component name="phy_onboard_1" display_name="Ethernet PHY 1" type="chip" sub_type="ethernet" major_group="Ethernet">
<description>Ethernet PHY 1 on the board not including reset/interrupt</description>
<component_modes>
<component_mode name="rgmii" display_name="RGMII mode">
<interfaces>
<interface name="rgmii_1" order="0"/>
<interface name="mdio" order="1"/>
</interfaces>
</component_mode>
</component_modes>
</component>
<component name="phy_onboard_2" display_name="Ethernet PHY 2" type="chip" sub_type="ethernet" major_group="Ethernet">
<description>Ethernet PHY 2 on the board not including reset/interrupt</description>
<component_modes>
<component_mode name="rgmii" display_name="RGMII mode">
<interfaces>
<interface name="rgmii_2" order="0"/>
</interfaces>
</component_mode>
</component_modes>
</component>
<component name="phy_onboard_3" display_name="Ethernet PHY 3" type="chip" sub_type="ethernet" major_group="Ethernet">
<description>Ethernet PHY 3 on the board not including reset/interrupt</description>
<component_modes>
<component_mode name="rgmii" display_name="RGMII mode">
<interfaces>
<interface name="rgmii_3" order="0"/>
</interfaces>
</component_mode>
</component_modes>
</component>
<component name="phy_onboard_4" display_name="Ethernet PHY 4" type="chip" sub_type="ethernet" major_group="Ethernet">
<description>Ethernet PHY 4 on the board not including reset/interrupt</description>
<component_modes>
<component_mode name="rgmii" display_name="RGMII mode">
<interfaces>
<interface name="rgmii_4" order="0"/>
</interfaces>
</component_mode>
</component_modes>
</component>
</components>
<connections>
<connection name="part0_sys_diff_clock" component1="part0" component2="sys_diff_clock">
<connection_map c1_st_index="1" c1_end_index="2" c2_st_index="0" c2_end_index="1"/>
</connection>
<connection name="part0_led_4bits" component1="part0" component2="led_4bits">
<connection_map c1_st_index="3" c1_end_index="6" c2_st_index="0" c2_end_index="3"/>
</connection>
<connection name="part0_push_button_4bits" component1="part0" component2="push_button_4bits">
<connection_map c1_st_index="7" c1_end_index="10" c2_st_index="0" c2_end_index="3"/>
</connection>
<connection name="part0_reset" component1="part0" component2="reset">
<connection_map c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
</connection>
<connection name="part0_pmod_usb_uart" component1="part0" component2="pmod_usb_uart">
<connection_map c1_st_index="11" c1_end_index="12" c2_st_index="0" c2_end_index="1"/>
</connection>
<connection name="part0_phy_onboard_1" component1="part0" component2="phy_onboard_1">
<connection_map name="part0_rgmii_1" c1_st_index="15" c1_end_index="26" c2_st_index="0" c2_end_index="11"/>
</connection>
<connection name="part0_phy_onboard_2" component1="part0" component2="phy_onboard_2">
<connection_map name="part0_rgmii_2" c1_st_index="27" c1_end_index="38" c2_st_index="0" c2_end_index="11"/>
</connection>
<connection name="part0_phy_onboard_3" component1="part0" component2="phy_onboard_3">
<connection_map name="part0_rgmii_3" c1_st_index="39" c1_end_index="50" c2_st_index="0" c2_end_index="11"/>
</connection>
<connection name="part0_phy_onboard_4" component1="part0" component2="phy_onboard_4">
<connection_map name="part0_rgmii_4" c1_st_index="51" c1_end_index="62" c2_st_index="0" c2_end_index="11"/>
</connection>
</connections>
</board>
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