-
Notifications
You must be signed in to change notification settings - Fork 0
Home
At start, we were expected to design and implement a processor which supports instruction set: (AND, ADD, LD, ST, ANDI, ADDI, CMP, JUMP, JE, JA, JB, JBE, JAE). Processor will have 12 bits address width and 16 bits data width. Processor will have 5 parts as follows. Register File will hold register values and signal to write into any register. There will be 16 registers in processor. Instruction Memory will be a read-only memory and instructions will be stored in this component. If the current instruction is not one of the JUMP instructions(JUMP, JE, JA etc.); the next instruction will be fetched and executed consecutively from this memory. Data Memory will be read-write memory which will store data. Program will be able to read data from data memory, and also store data to this memory. Data Memory will have 12 bits address width, and 16 bits data width. Control Unit will produce proper signals to all datapath components. For example if the instruction is ST, control unit should produce memWrite signal which will allow Data Memory component to write data value on its data input to the address on its address input. Arithmetic Logic Unit (ALU) will compute arithmetic operations ADD,AND,ADDI,ANDI. Operands will be fetched from register+register or register+ immediate value. Result will be stored to the Register File. Control unit should produce proper signals to ALU according to instruction opcode (Every instruction should have distinct operational code). Detailed information about instructions is given below.
ADD,AND will have same form.
ADD instruction will add two register, and store result into another register.Structure of instruction is:
ADD DST,SRC1,SRC2
where SRC1 and SRC2 are source registers, and DST is destination register for the operation.
ADDI,ANDI,ORI will have same form.
ADDI instruction will add a register value and immediate value, and store the result into another register.Form of instruction is:
ADDI DST,SRC1,IMM
where SRC1 is a register, DST is destination register and IMM is immediate value. IMM size will be max available size on processor's design.
JUMP instruction will set the Program Counter(PC will hold current instruction’s address) to the given value in the instruction.
JUMP OFFSET
where OFFSET will be in PC relative mode. OFFSET will be the offset for PC and it can be negative. For example:
JUMP 3 instruction will set PC to: next instructions address + 3( go forward 3 instruction)
JUMP -5 instruction will set PC to: next instructions address – 5 (go back 5 instruction)
LD instruction will load a value from Data Memory to any register.
LD DST,ADDR
where DST is a register to load and ADDR is a address in max available bit size. Upper bits of ADDR will be zero extended.
ST instruction will store value from a register to Data Memory.
ST SRC,ADDR
where SRC is a register to fetch data and ADDR is a Data Memory address to store content of the register. Upper bits of ADDR will be zero extended.
Compare instruction will compare two operands, then will update the flag values of zero flag ZF and carry flag CF. Following conditional jump instruction will set the destination address if the condition holds.
CMP OP1,OP2
will compare registers OP1 and OP2 if they are equal, flag values will be ZF=1, CF=0, if the first operands value is greater flag values will be ZF=0, CF=0, if the first operands value is less than the second operand flag values will be ZF=0,CF=1.
As in the JUMP instruction, but conditional with the flag values, JE, JA, JB, JAE, JBE jumps to a new destination address.
JE ADDR If flag values are (ZF=1, CF=0), PC will be set to ADDR(PC-relative).
JA ADDR If flag values are (ZF=0, CF=0), PC will be set to ADDR(PC-relative).
JB ADDR If flag values are (ZF=0, CF=1), PC will be set to ADDR(PC-relative).
JAE ADDR If flag values are (CF=0), PC will be set to ADDR(PC-relative).
JBE ADDR If flag values are (CF=1 or ZF=1), PC will be set to ADDR(PC-relative).
The design process includes; instruction set architecture and control unit design. For instruction set architecture we needed to decide on fields of our instruction like, what will be the size of opcode field? How many bits to reserve for register addressing in instruction? What is the maximum possible size for immediate part? Control unit design will include proper signal generation for all datapath. Firstly, we should define a Finite State Machine for our processor. For every instruction we should decide, how many states an instruction will need to execute? What will be the control signals for each state of an instruction?
For example LD instruction will do following operations consecutively:
• Read PC value
• Fetch instruction from Instruction Memory with address given in PC
• Read Data Memory with given address in instruction
• Write content from Data Memory to destination register.
LD instruction will require 4 states to complete. At each state some signals should control components to do right operations. For example at state 1, PCread signal, which will allow PC to put its content on its output, should be activated. Remember that PC is a 12 bit register which holds the current instructions address. At state 2, instruction fetch, instruction will be fetched from Instruction Memory. Therefore, instRead signal will be activated. At state 3, extended address will be put on address input of Data Memory, and dataMemRead signal will be activated. At state 4, we will write output from Data Memory to the register given in instruction. So, regWrite signal will be activated. Also we need to consider, full Datapath will contain additional combinatorial components like multiplexer,adder, ALU. Control signals have to be designed also for these parts of processor. For example, if current instruction is not setting PC value(not one of JUMP instructions), next PC value will be PC+1. Since there is two possible next value for PC, there should be a multiplexer at input of PC register with two inputs: PC+1 and PC relative calculated address from instructions JUMP group. We should produce a signal for this multiplexer Pcselect signal. Our design must include following signals also.
ALUcontrol signal should select operation on the Arithmetic Logic Unit (ALU). For example there are 2 arithmetic or logic operation on ALU(AND, ADD, ANDI, ADDI). ALUcontrol must be at least 2 bits and for every operation 2 bit value has to be assigned.
MemWrite signal must be 1 for the final state of ST instruction.
PCwrite signal at the final state of JUMP instructions, PC will be modified. PCwrite signal must be 1.
Firstly we need to design instruction set architecture(ISA). We draw ISA using Excel. When the details are clear about the processor, we could write an assembler to produce machine code input for this processor. Assembler will convert given mnemonics to the binary codes. We used Java for the assembler. In assembly language refer registers as R0,R1... R7. Some example instructions:
ADD R5,R0,R2 // which will do R5=R0+R2
ADDI R3,R1,12 // which will do R3=R1+Extend[12]
LD R5,12 // which will do R5=DataMemory[Extend[12]]
Assembler input will be a code sequence of assembly language given in above instruction set. Conversion of mnemonics to .hex output will depend ISA. Since our processor is 16 bits, for each instruction assembler should output 4 digit hexadecimal number like following:
4000
4202
8440
8683
C60A
86EC
2801
2063
A000
This output file will be input to our Logism and Verilog designs. Logisim memory file with above machine code looks like:
v2.0 raw
4000 4202 8440 8683 c60a 86ec 2801 2063 a000
Verilog memory file doesn't require any header like in logisim(v2.0 raw). It will be in .hex file format and content will be same as the generated machine code. Verilog code to read memory from a .hex file:
module memory(); reg [15:0] InstructionMemory [15:0]; initial begin
$readmemh("AssemblerOutput.hex", InstructionMemory); end
endmodule
Data Memory can be read the same way for both Verilog and Logisim design. Data will be entered to Data Memory files manually.
We were required to design our processor on Logisim schematic design software. We are expected to write an assembly code with all instructions defined above. Then, our assembler will convert assembly code to machine code which will be input for logisim design. So we can load this machine code to the Instruction Memory by right clicking on Memory component on Logisim software.
We were required to design our processor on Verilog HDL as final part. Each component in the design should be defined as a module in Verilog HDL. Our assemblers machine code output will be input for the Verilog design. We were responsible for generating test instructions, testing and debugging your design on ModelSim software.