[X86][CodeGen] Convert masked.load/store to CLOAD/CSTORE node only wh…

…en vector size = 1 This fixes the crash when building llvm-test-suite with avx512f + cf.
Ericsson · Jul 5, 2024 · a48305e · a48305e
1 parent 27bb2a3
commit a48305e
Show file tree

Hide file tree

Showing 3 changed files with 30 additions and 7 deletions.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4798,8 +4798,8 @@ void SelectionDAGBuilder::visitMaskedStore(const CallInst &I,
   const auto &TTI =
       TLI.getTargetMachine().getTargetTransformInfo(*I.getFunction());
   SDValue StoreNode =
-      !IsCompressing && TTI.hasConditionalLoadStoreForType(
-                            I.getArgOperand(0)->getType()->getScalarType())
+      !IsCompressing &&
+              TTI.hasConditionalLoadStoreForType(I.getArgOperand(0)->getType())
           ? TLI.visitMaskedStore(DAG, sdl, getMemoryRoot(), MMO, Ptr, Src0,
                                  Mask)
           : DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask,
@@ -4984,8 +4984,8 @@ void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
   // variables.
   SDValue Load;
   SDValue Res;
-  if (!IsExpanding && TTI.hasConditionalLoadStoreForType(
-                          Src0Operand->getType()->getScalarType()))
+  if (!IsExpanding &&
+      TTI.hasConditionalLoadStoreForType(Src0Operand->getType()))
     Res = TLI.visitMaskedLoad(DAG, sdl, InChain, MMO, Load, Ptr, Src0, Mask);
   else
     Res = Load =

diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -185,9 +185,11 @@ bool X86TTIImpl::hasConditionalLoadStoreForType(Type *Ty) const {
   // 16/32/64-bit operands.
   // TODO: Support f32/f64 with VMOVSS/VMOVSD with zero mask when it's
   // profitable.
-  if (!Ty->isIntegerTy())
+  auto *VTy = dyn_cast<FixedVectorType>(Ty);
+  if (!Ty->isIntegerTy() && (!VTy || VTy->getNumElements() != 1))
     return false;
-  switch (cast<IntegerType>(Ty)->getBitWidth()) {
+  auto *ScalarTy = Ty->getScalarType();
+  switch (cast<IntegerType>(ScalarTy)->getBitWidth()) {
   default:
     return false;
   case 16:

diff --git a/llvm/test/CodeGen/X86/apx/cf.ll b/llvm/test/CodeGen/X86/apx/cf.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64 -mattr=+cf -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64 -mattr=+cf,+avx512f -verify-machineinstrs | FileCheck %s
 
 define void @basic(i32 %a, ptr %b, ptr %p, ptr %q) {
 ; CHECK-LABEL: basic:
@@ -103,3 +103,24 @@ entry:
   %2 = bitcast <1 x i64> %1 to i64
   ret i64 %2
 }
+
+define void @no_crash(ptr %p, <4 x i1> %cond1, <4 x i1> %cond2) {
+; CHECK-LABEL: no_crash:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpslld $31, %xmm1, %xmm1
+; CHECK-NEXT:    vptestmd %zmm1, %zmm1, %k0
+; CHECK-NEXT:    kshiftlw $12, %k0, %k0
+; CHECK-NEXT:    kshiftrw $12, %k0, %k1
+; CHECK-NEXT:    vpslld $31, %xmm0, %xmm0
+; CHECK-NEXT:    vptestmd %zmm0, %zmm0, %k0
+; CHECK-NEXT:    kshiftlw $12, %k0, %k0
+; CHECK-NEXT:    kshiftrw $12, %k0, %k2
+; CHECK-NEXT:    vmovdqu64 (%rdi), %zmm0 {%k2} {z}
+; CHECK-NEXT:    vmovdqu64 %zmm0, (%rdi) {%k1}
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+entry:
+  %0 = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr %p, i32 8, <4 x i1> %cond1, <4 x i64> poison)
+  call void @llvm.masked.store.v4i64.p0(<4 x i64> %0, ptr %p, i32 8, <4 x i1> %cond2)
+  ret void
+}