Update

Logic_Analyzer.PrjPcb → Hardware/Logic_Analyzer.PrjPcb

@@ -57,7 +57,7 @@ GenerateClassCluster=0
 DocumentUniqueId=ELLMIDNE
 
 [Document2]
-DocumentPath=Logic_Analyzer.PcbDoc
+DocumentPath=Logic_Analyzer_ASCII.PcbDoc
 AnnotationEnabled=1
 AnnotateStartValue=1
 AnnotationIndexControlEnabled=0
@@ -1008,6 +1008,14 @@ DItemRevisionGUID=
 GenerateClassCluster=0
 DocumentUniqueId=
 
+[GeneratedDocument1]
+DocumentPath=Project Outputs for Logic_Analyzer\Design Rule Check - Logic_Analyzer.html
+DItemRevisionGUID=
+
+[GeneratedDocument2]
+DocumentPath=Project Outputs for Logic_Analyzer\Design Rule Check - Logic_Analyzer_ASCII.html
+DItemRevisionGUID=
+
 [Configuration1]
 Name=Sources
 ParameterCount=0

Hardware/Logic_Analyzer.PrjPcbStructure

@@ -0,0 +1 @@
+Record=TopLevelDocument|FileName=Logic_Analyzer.SchDoc|SheetNumber=1

Hardware/Project Logs for Logic_Analyzer/Logic_Analyzer PCB ECO 2021-11-5 10-22-27.LOG

@@ -0,0 +1,10 @@
+Removed Pin From Net: NetName=NetJ2_5 Pin=R12-5
+Removed Pin From Net: NetName=NetJ2_4 Pin=R12-6
+Removed Pin From Net: NetName=NetJ2_3 Pin=R12-7
+Removed Pin From Net: NetName=NetJ2_2 Pin=R12-8
+Added Pin To Net: NetName=NetJ2_2 Pin=R12-5
+Added Pin To Net: NetName=NetJ2_3 Pin=R12-6
+Added Pin To Net: NetName=NetJ2_4 Pin=R12-7
+Added Pin To Net: NetName=NetJ2_5 Pin=R12-8
+Added Member To Class: ClassName=Logic_Analyzer Member=Component R10 100K
+Added Member To Class: ClassName=Logic_Analyzer Member=Component R13 100K

Hardware/Project Logs for Logic_Analyzer/Logic_Analyzer PCB ECO 2021-11-5 11-17-22.LOG

@@ -0,0 +1,9 @@
+Removed Pin From Net: NetName=NetJ2_5 Pin=R12-5
+Removed Pin From Net: NetName=NetJ2_4 Pin=R12-6
+Removed Pin From Net: NetName=NetJ2_3 Pin=R12-7
+Removed Pin From Net: NetName=NetJ2_2 Pin=R12-8
+Added Pin To Net: NetName=NetJ2_2 Pin=R12-5
+Added Pin To Net: NetName=NetJ2_3 Pin=R12-6
+Added Pin To Net: NetName=NetJ2_4 Pin=R12-7
+Added Pin To Net: NetName=NetJ2_5 Pin=R12-8
+Added Member To Class: ClassName=Logic_Analyzer Member=Component R10 100K

Hardware/Project Outputs for Logic_Analyzer/Design Rule Check - Logic_Analyzer.drc

@@ -0,0 +1,48 @@
+Protel Design System Design Rule Check
+PCB File : F:\Desktop\Logic_Analyzer\Logic_Analyzer.PcbDoc
+Date     : 2021/11/5
+Time     : 16:01:26
+
+Processing Rule : Clearance Constraint (Gap=0.127mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
+Rule Violations :0
+
+Processing Rule : Un-Routed Net Constraint ( (All) )
+Rule Violations :0
+
+Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
+Rule Violations :0
+
+Processing Rule : Width Constraint (Min=0.089mm) (Max=0.762mm) (Preferred=0.254mm) (All)
+Rule Violations :0
+
+Processing Rule : Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
+Rule Violations :0
+
+Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
+Rule Violations :0
+
+Processing Rule : Hole To Hole Clearance (Gap=0.254mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Minimum Solder Mask Sliver (Gap=0mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Silk To Solder Mask (Clearance=0mm) (IsPad),(All)
+Rule Violations :0
+
+Processing Rule : Silk to Silk (Clearance=0.254mm) (All),(All)
+Rule Violations :0
+
+Processing Rule : Net Antennae (Tolerance=0mm) (All)
+Rule Violations :0
+
+Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
+Rule Violations :0
+
+
+Violations Detected : 0
+Waived Violations : 0
+Time Elapsed        : 00:00:02