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stable_21.11.x.FOME: backup domain reset re: FOME_STM32_LSE_MAX_WAIT #2

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stable_21.11.x.FOME: backup domain reset re: FOME_STM32_LSE_MAX_WAIT #2

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10 changes: 9 additions & 1 deletion os/hal/ports/STM32/STM32F0xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,15 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP;

/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if (
#if STM32_LSE_ENABLED
(
fomeLseCounter >= FOME_STM32_LSE_MAX_WAIT
&& (RCC->BDCR & STM32_RTCSEL_MASK) != FOME_STM32_LSE_WAIT_MAX_RTCSEL
) || fomeLseCounter < FOME_STM32_LSE_MAX_WAIT
&&
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@nmschulte nmschulte Jan 16, 2025

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I need to test building with these patches, but am concerned I might need parens around the sides of && here, which means reworking the macros/code as I can tell at the moment.

#endif
(RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
Expand Down
10 changes: 9 additions & 1 deletion os/hal/ports/STM32/STM32F1xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,15 @@ static void hal_lld_backup_domain_init(void) {

#if HAL_USE_RTC
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if (
#if STM32_LSE_ENABLED
(
fomeLseCounter >= FOME_STM32_LSE_MAX_WAIT
&& (RCC->BDCR & STM32_RTCSEL_MASK) != FOME_STM32_LSE_WAIT_MAX_RTCSEL
) || fomeLseCounter < FOME_STM32_LSE_MAX_WAIT
&&
#endif
(RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
Expand Down
10 changes: 9 additions & 1 deletion os/hal/ports/STM32/STM32F37x/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,15 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP;

/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if (
#if STM32_LSE_ENABLED
(
fomeLseCounter >= FOME_STM32_LSE_MAX_WAIT
&& (RCC->BDCR & STM32_RTCSEL_MASK) != FOME_STM32_LSE_WAIT_MAX_RTCSEL
) || fomeLseCounter < FOME_STM32_LSE_MAX_WAIT
&&
#endif
(RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
Expand Down
10 changes: 9 additions & 1 deletion os/hal/ports/STM32/STM32F3xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,15 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP;

/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if (
#if STM32_LSE_ENABLED
(
fomeLseCounter >= FOME_STM32_LSE_MAX_WAIT
&& (RCC->BDCR & STM32_RTCSEL_MASK) != FOME_STM32_LSE_WAIT_MAX_RTCSEL
) || fomeLseCounter < FOME_STM32_LSE_MAX_WAIT
&&
#endif
(RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
Expand Down
10 changes: 9 additions & 1 deletion os/hal/ports/STM32/STM32F4xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,15 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP;

/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if (
#if STM32_LSE_ENABLED
(
fomeLseCounter >= FOME_STM32_LSE_MAX_WAIT
&& (RCC->BDCR & STM32_RTCSEL_MASK) != FOME_STM32_LSE_WAIT_MAX_RTCSEL
) || fomeLseCounter < FOME_STM32_LSE_MAX_WAIT
&&
#endif
(RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
Expand Down
10 changes: 9 additions & 1 deletion os/hal/ports/STM32/STM32F7xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,15 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR1 |= PWR_CR1_DBP;

/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if (
#if STM32_LSE_ENABLED
(
fomeLseCounter >= FOME_STM32_LSE_MAX_WAIT
&& (RCC->BDCR & STM32_RTCSEL_MASK) != FOME_STM32_LSE_WAIT_MAX_RTCSEL
) || fomeLseCounter < FOME_STM32_LSE_MAX_WAIT
&&
#endif
(RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
Expand Down
10 changes: 9 additions & 1 deletion os/hal/ports/STM32/STM32H7xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,15 @@ static inline void init_bkp_domain(void) {
PWR->CR1 |= PWR_CR1_DBP;

/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if (
#if STM32_LSE_ENABLED
(
fomeLseCounter >= FOME_STM32_LSE_MAX_WAIT
&& (RCC->BDCR & STM32_RTCSEL_MASK) != FOME_STM32_LSE_WAIT_MAX_RTCSEL
) || fomeLseCounter < FOME_STM32_LSE_MAX_WAIT
&&
#endif
(RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
Expand Down
10 changes: 9 additions & 1 deletion os/hal/ports/STM32/STM32L0xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,15 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP;

/* Reset BKP domain if different clock source selected.*/
if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if (
#if STM32_LSE_ENABLED
(
fomeLseCounter >= FOME_STM32_LSE_MAX_WAIT
&& (RCC->CSR & STM32_RTCSEL_MASK) != FOME_STM32_LSE_WAIT_MAX_RTCSEL
) || fomeLseCounter < FOME_STM32_LSE_MAX_WAIT
&&
#endif
(RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->CSR |= RCC_CSR_RTCRST;
RCC->CSR &= ~RCC_CSR_RTCRST;
Expand Down
10 changes: 9 additions & 1 deletion os/hal/ports/STM32/STM32L1xx/hal_lld.c
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,15 @@ static void hal_lld_backup_domain_init(void) {
PWR->CR |= PWR_CR_DBP;

/* Reset BKP domain if different clock source selected.*/
if ((RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
if (
#if STM32_LSE_ENABLED
(
fomeLseCounter >= FOME_STM32_LSE_MAX_WAIT
&& (RCC->CSR & STM32_RTCSEL_MASK) != FOME_STM32_LSE_WAIT_MAX_RTCSEL
) || fomeLseCounter < FOME_STM32_LSE_MAX_WAIT
&&
#endif
(RCC->CSR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
RCC->CSR |= RCC_CSR_RTCRST;
RCC->CSR &= ~RCC_CSR_RTCRST;
Expand Down