GitHub - FPGAOL-CE/AXISoCQuadCoreModule: sample project for openxc7

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
signals		signals
.gitignore		.gitignore
AXISoCQuadCoreModule_TopLevel.v		AXISoCQuadCoreModule_TopLevel.v
AXISoCQuadCoreModule_TopLevel_Buttons.v		AXISoCQuadCoreModule_TopLevel_Buttons.v
AXISoCQuadCoreModule_TopLevel_Buttons_axiSlave.v		AXISoCQuadCoreModule_TopLevel_Buttons_axiSlave.v
AXISoCQuadCoreModule_TopLevel_CPU0.v		AXISoCQuadCoreModule_TopLevel_CPU0.v
AXISoCQuadCoreModule_TopLevel_CPU0_CPU.v		AXISoCQuadCoreModule_TopLevel_CPU0_CPU.v
AXISoCQuadCoreModule_TopLevel_CPU0_CPU_ALU.v		AXISoCQuadCoreModule_TopLevel_CPU0_CPU_ALU.v
AXISoCQuadCoreModule_TopLevel_CPU0_CPU_CMP.v		AXISoCQuadCoreModule_TopLevel_CPU0_CPU_CMP.v
AXISoCQuadCoreModule_TopLevel_CPU0_CPU_ID.v		AXISoCQuadCoreModule_TopLevel_CPU0_CPU_ID.v
AXISoCQuadCoreModule_TopLevel_CPU0_CPU_Regs.v		AXISoCQuadCoreModule_TopLevel_CPU0_CPU_Regs.v
AXISoCQuadCoreModule_TopLevel_CPU0_CPU_State_CSR.hex		AXISoCQuadCoreModule_TopLevel_CPU0_CPU_State_CSR.hex
AXISoCQuadCoreModule_TopLevel_CPU0_Master.v		AXISoCQuadCoreModule_TopLevel_CPU0_Master.v
AXISoCQuadCoreModule_TopLevel_CPU1.v		AXISoCQuadCoreModule_TopLevel_CPU1.v
AXISoCQuadCoreModule_TopLevel_CPU1_CPU.v		AXISoCQuadCoreModule_TopLevel_CPU1_CPU.v
AXISoCQuadCoreModule_TopLevel_CPU1_CPU_ALU.v		AXISoCQuadCoreModule_TopLevel_CPU1_CPU_ALU.v
AXISoCQuadCoreModule_TopLevel_CPU1_CPU_CMP.v		AXISoCQuadCoreModule_TopLevel_CPU1_CPU_CMP.v
AXISoCQuadCoreModule_TopLevel_CPU1_CPU_ID.v		AXISoCQuadCoreModule_TopLevel_CPU1_CPU_ID.v
AXISoCQuadCoreModule_TopLevel_CPU1_CPU_Regs.v		AXISoCQuadCoreModule_TopLevel_CPU1_CPU_Regs.v
AXISoCQuadCoreModule_TopLevel_CPU1_CPU_State_CSR.hex		AXISoCQuadCoreModule_TopLevel_CPU1_CPU_State_CSR.hex
AXISoCQuadCoreModule_TopLevel_CPU1_Master.v		AXISoCQuadCoreModule_TopLevel_CPU1_Master.v
AXISoCQuadCoreModule_TopLevel_CPU2.v		AXISoCQuadCoreModule_TopLevel_CPU2.v
AXISoCQuadCoreModule_TopLevel_CPU2_CPU.v		AXISoCQuadCoreModule_TopLevel_CPU2_CPU.v
AXISoCQuadCoreModule_TopLevel_CPU2_CPU_ALU.v		AXISoCQuadCoreModule_TopLevel_CPU2_CPU_ALU.v
AXISoCQuadCoreModule_TopLevel_CPU2_CPU_CMP.v		AXISoCQuadCoreModule_TopLevel_CPU2_CPU_CMP.v
AXISoCQuadCoreModule_TopLevel_CPU2_CPU_ID.v		AXISoCQuadCoreModule_TopLevel_CPU2_CPU_ID.v
AXISoCQuadCoreModule_TopLevel_CPU2_CPU_Regs.v		AXISoCQuadCoreModule_TopLevel_CPU2_CPU_Regs.v
AXISoCQuadCoreModule_TopLevel_CPU2_CPU_State_CSR.hex		AXISoCQuadCoreModule_TopLevel_CPU2_CPU_State_CSR.hex
AXISoCQuadCoreModule_TopLevel_CPU2_Master.v		AXISoCQuadCoreModule_TopLevel_CPU2_Master.v
AXISoCQuadCoreModule_TopLevel_CPU3.v		AXISoCQuadCoreModule_TopLevel_CPU3.v
AXISoCQuadCoreModule_TopLevel_CPU3_CPU.v		AXISoCQuadCoreModule_TopLevel_CPU3_CPU.v
AXISoCQuadCoreModule_TopLevel_CPU3_CPU_ALU.v		AXISoCQuadCoreModule_TopLevel_CPU3_CPU_ALU.v
AXISoCQuadCoreModule_TopLevel_CPU3_CPU_CMP.v		AXISoCQuadCoreModule_TopLevel_CPU3_CPU_CMP.v
AXISoCQuadCoreModule_TopLevel_CPU3_CPU_ID.v		AXISoCQuadCoreModule_TopLevel_CPU3_CPU_ID.v
AXISoCQuadCoreModule_TopLevel_CPU3_CPU_Regs.v		AXISoCQuadCoreModule_TopLevel_CPU3_CPU_Regs.v
AXISoCQuadCoreModule_TopLevel_CPU3_CPU_State_CSR.hex		AXISoCQuadCoreModule_TopLevel_CPU3_CPU_State_CSR.hex
AXISoCQuadCoreModule_TopLevel_CPU3_Master.v		AXISoCQuadCoreModule_TopLevel_CPU3_Master.v
AXISoCQuadCoreModule_TopLevel_CPUExtReset.v		AXISoCQuadCoreModule_TopLevel_CPUExtReset.v
AXISoCQuadCoreModule_TopLevel_CPUExtReset_axiSlave.v		AXISoCQuadCoreModule_TopLevel_CPUExtReset_axiSlave.v
AXISoCQuadCoreModule_TopLevel_Reg0.v		AXISoCQuadCoreModule_TopLevel_Reg0.v
AXISoCQuadCoreModule_TopLevel_Reg0_axiSlave.v		AXISoCQuadCoreModule_TopLevel_Reg0_axiSlave.v
AXISoCQuadCoreModule_TopLevel_Reg1.v		AXISoCQuadCoreModule_TopLevel_Reg1.v
AXISoCQuadCoreModule_TopLevel_Reg1_axiSlave.v		AXISoCQuadCoreModule_TopLevel_Reg1_axiSlave.v
AXISoCQuadCoreModule_TopLevel_Reg2.v		AXISoCQuadCoreModule_TopLevel_Reg2.v
AXISoCQuadCoreModule_TopLevel_Reg2_axiSlave.v		AXISoCQuadCoreModule_TopLevel_Reg2_axiSlave.v
AXISoCQuadCoreModule_TopLevel_Reg3.v		AXISoCQuadCoreModule_TopLevel_Reg3.v
AXISoCQuadCoreModule_TopLevel_Reg3_axiSlave.v		AXISoCQuadCoreModule_TopLevel_Reg3_axiSlave.v
AXISoCQuadCoreModule_TopLevel_Switches.v		AXISoCQuadCoreModule_TopLevel_Switches.v
AXISoCQuadCoreModule_TopLevel_Switches_axiSlave.v		AXISoCQuadCoreModule_TopLevel_Switches_axiSlave.v
AXISoCQuadCoreModule_TopLevel_cpu0AutoDecrementRegister.v		AXISoCQuadCoreModule_TopLevel_cpu0AutoDecrementRegister.v
AXISoCQuadCoreModule_TopLevel_cpu0AutoDecrementRegister_axiSlave.v		AXISoCQuadCoreModule_TopLevel_cpu0AutoDecrementRegister_axiSlave.v
AXISoCQuadCoreModule_TopLevel_cpu0AutoIncrementCounter.v		AXISoCQuadCoreModule_TopLevel_cpu0AutoIncrementCounter.v
AXISoCQuadCoreModule_TopLevel_cpu0AutoIncrementCounter_axiSlave.v		AXISoCQuadCoreModule_TopLevel_cpu0AutoIncrementCounter_axiSlave.v
AXISoCQuadCoreModule_TopLevel_cpu0IOGateway.v		AXISoCQuadCoreModule_TopLevel_cpu0IOGateway.v
AXISoCQuadCoreModule_TopLevel_cpu0IOGateway_readAddress.v		AXISoCQuadCoreModule_TopLevel_cpu0IOGateway_readAddress.v
AXISoCQuadCoreModule_TopLevel_cpu0IOGateway_writeAddress.v		AXISoCQuadCoreModule_TopLevel_cpu0IOGateway_writeAddress.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_DuplexMux.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_DuplexMux.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_Encoder.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_Encoder.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_TransactionDetectors0.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_TransactionDetectors0.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_TransactionDetectors1.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_TransactionDetectors1.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_encoder.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_encoder.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors0.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors0.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors1.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors1.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors2.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors2.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors3.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors3.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors4.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray0_rangeDetectors4.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_encoder.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_encoder.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors0.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors0.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors1.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors1.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors2.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors2.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors3.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors3.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors4.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_readInterconnect_rangeDetectorArray1_rangeDetectors4.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_DuplexMux.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_DuplexMux.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_Encoder.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_Encoder.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_TransactionDetectors0.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_TransactionDetectors0.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_TransactionDetectors1.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_TransactionDetectors1.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_encoder.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_encoder.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors0.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors0.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors1.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors1.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors2.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors2.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors3.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors3.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors4.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray0_rangeDetectors4.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_encoder.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_encoder.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors0.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors0.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors1.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors1.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors2.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors2.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors3.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors3.v
AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors4.v		AXISoCQuadCoreModule_TopLevel_cpu0Interconnect_writeInterconnect_rangeDetectorArray1_rangeDetectors4.v
AXISoCQuadCoreModule_TopLevel_cpu0Memory.v		AXISoCQuadCoreModule_TopLevel_cpu0Memory.v
AXISoCQuadCoreModule_TopLevel_cpu0Memory_State_buff0.hex		AXISoCQuadCoreModule_TopLevel_cpu0Memory_State_buff0.hex
AXISoCQuadCoreModule_TopLevel_cpu0Memory_State_buff1.hex		AXISoCQuadCoreModule_TopLevel_cpu0Memory_State_buff1.hex
AXISoCQuadCoreModule_TopLevel_cpu0Memory_State_buff2.hex		AXISoCQuadCoreModule_TopLevel_cpu0Memory_State_buff2.hex
AXISoCQuadCoreModule_TopLevel_cpu0Memory_State_buff3.hex		AXISoCQuadCoreModule_TopLevel_cpu0Memory_State_buff3.hex

FPGAOL-CE/AXISoCQuadCoreModule

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