bsp: Improve async serial driver

The CMSIS6 has an IRQ driven CMSIS compliant UART driver. USART0 is set to non-secure. TX/RX are now also turned ON at initialization of the USART. Because the driver is IRQ driven, the send function only initiates the transaction. To maintain the CMSIS5 operation model, a busy wait for the completion of the send operation is required. Signed-off-by: Dávid Házi <[email protected]>
FreeRTOS · Feb 28, 2024 · 6c8a4c7 · 6c8a4c7
1 parent 45ad77e
commit 6c8a4c7
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Showing 5 changed files with 426 additions and 3 deletions.
diff --git a/bsp/CMakeLists.txt b/bsp/CMakeLists.txt
@@ -143,6 +143,12 @@ target_sources(toolchain-override
         $<$<VERSION_GREATER_EQUAL:${ARM_GNU_TOOLCHAIN_VERSION},11.3.1>:${CMAKE_CURRENT_LIST_DIR}/common/syscalls_stub.c>
 )
 
+target_include_directories(arm-corstone-platform-bsp
+    PUBLIC
+        $<$<STREQUAL:${ARM_CORSTONE_BSP_TARGET_PLATFORM},corstone300>:${CMAKE_CURRENT_LIST_DIR}/corstone300/include>
+        $<$<STREQUAL:${ARM_CORSTONE_BSP_TARGET_PLATFORM},corstone310>:${CMAKE_CURRENT_LIST_DIR}/corstone310/include>
+)
+
 # BSP serial library
 
 add_library(fri-bsp STATIC)
@@ -155,8 +161,6 @@ target_sources(fri-bsp
 
 target_include_directories(fri-bsp
     PUBLIC
-        $<$<STREQUAL:${ARM_CORSTONE_BSP_TARGET_PLATFORM},corstone300>:${CMAKE_CURRENT_LIST_DIR}/corstone300/include>
-        $<$<STREQUAL:${ARM_CORSTONE_BSP_TARGET_PLATFORM},corstone310>:${CMAKE_CURRENT_LIST_DIR}/corstone310/include>
         common
 )
 

diff --git a/bsp/common/bsp_serial.c b/bsp/common/bsp_serial.c
@@ -1,4 +1,4 @@
-/* Copyright 2017-2023 Arm Limited and/or its affiliates
+/* Copyright 2017-2024 Arm Limited and/or its affiliates
  * <[email protected]>
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,7 +43,10 @@ static void prvWriteChars( int fd,
 void bsp_serial_init( void )
 {
     Driver_USART0.Initialize( NULL );
+    Driver_USART0.PowerControl( ARM_POWER_FULL );
     Driver_USART0.Control( ARM_USART_MODE_ASYNCHRONOUS, DEFAULT_UART_BAUDRATE );
+    Driver_USART0.Control( ARM_USART_CONTROL_TX, 1 );
+    Driver_USART0.Control( ARM_USART_CONTROL_RX, 1 );
 
     if( xLoggingMutex == NULL )
     {
@@ -55,6 +58,10 @@ void bsp_serial_init( void )
 void bsp_serial_print( char * str )
 {
     ( void ) Driver_USART0.Send( str, strlen( str ) );
+
+    while( Driver_USART0.GetTxCount() != strlen( str ) )
+    {
+    }
 }
 
 #if defined( __ARMCOMPILER_VERSION )
@@ -203,6 +210,10 @@ static void prvWriteChars( int fd,
 
     bool allCharsWritten = ( bool ) ( Driver_USART0.Send( str, len ) == ARM_DRIVER_OK );
 
+    while( Driver_USART0.GetTxCount() != len )
+    {
+    }
+
     ( void ) xSemaphoreGive( xLoggingMutex );
 
     if( allCharsWritten == true )

diff --git a/bsp/corstone300/include/device_cfg.h b/bsp/corstone300/include/device_cfg.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2020-2024 Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __DEVICE_CFG_H__
+#define __DEVICE_CFG_H__
+
+#include "RTE_Components.h"
+
+/**
+ * \file device_cfg.h
+ * \brief Configuration file native driver re-targeting
+ *
+ * \details This file can be used to add native driver specific macro
+ *          definitions to select which peripherals are available in the build.
+ *
+ * This is a default device configuration file with all peripherals enabled.
+ */
+
+/* Secure only peripheral configuration */
+
+/* ARM MPS3 IO SCC */
+#ifdef RTE_MPS3_IO
+    #define MPS3_IO_NS
+    #define MPS3_IO_DEV    MPS3_IO_DEV_NS
+#endif
+
+/* I2C_SBCon */
+#ifdef RTE_I2C0
+    #define I2C0_SBCON_S
+    #define I2C0_SBCON_DEV    I2C0_SBCON_DEV_S
+#endif
+
+/* I2S */
+#ifdef RTE_I2S
+    #define MPS3_I2S_S
+    #define MPS3_I2S_DEV    MPS3_I2S_DEV_S
+#endif
+
+/* ARM UART Controller CMSDK */
+#ifdef RTE_USART0
+    #define UART0_CMSDK_NS
+    #define UART0_CMSDK_DEV    UART0_CMSDK_DEV_NS
+#endif
+#ifdef RTE_USART1
+    #define UART1_CMSDK_S
+    #define UART1_CMSDK_DEV      UART1_CMSDK_DEV_S
+#endif
+
+#define DEFAULT_UART_BAUDRATE    115200U
+
+/* To be used as CODE and DATA sram */
+#ifdef RTE_ISRAM0_MPC
+    #define MPC_ISRAM0_S
+    #define MPC_ISRAM0_DEV    MPC_ISRAM0_DEV_S
+#endif
+
+#ifdef RTE_ISRAM1_MPC
+    #define MPC_ISRAM1_S
+    #define MPC_ISRAM1_DEV    MPC_ISRAM0_DEV_S
+#endif
+
+#ifdef RTE_SRAM_MPC
+    #define MPC_SRAM_S
+    #define MPC_SRAM_DEV    MPC_SRAM_DEV_S
+#endif
+
+#ifdef RTE_QSPI_MPC
+    #define MPC_QSPI_S
+    #define MPC_QSPI_DEV    MPC_QSPI_DEV_S
+#endif
+
+/** System Counter Armv8-M */
+#ifdef RTE_SYSCOUNTER
+    #define SYSCOUNTER_CNTRL_ARMV8_M_S
+    #define SYSCOUNTER_CNTRL_ARMV8_M_DEV               SYSCOUNTER_CNTRL_ARMV8_M_DEV_S
+
+    #define SYSCOUNTER_READ_ARMV8_M_S
+    #define SYSCOUNTER_READ_ARMV8_M_DEV                SYSCOUNTER_READ_ARMV8_M_DEV_S
+
+/**
+ * Arbitrary scaling values for test purposes
+ */
+    #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT      1u
+    #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT    0u
+    #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT      1u
+    #define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT    0u
+#endif /* ifdef RTE_SYSCOUNTER */
+
+/* System timer */
+#ifdef RTE_TIMEOUT
+    #define SYSTIMER0_ARMV8_M_S
+    #define SYSTIMER0_ARMV8_M_DEV               SYSTIMER0_ARMV8_M_DEV_S
+    #define SYSTIMER1_ARMV8_M_S
+    #define SYSTIMER1_ARMV8_M_DEV               SYSTIMER1_ARMV8_M_DEV_S
+    #define SYSTIMER2_ARMV8_M_S
+    #define SYSTIMER2_ARMV8_M_DEV               SYSTIMER2_ARMV8_M_DEV_S
+    #define SYSTIMER3_ARMV8_M_S
+    #define SYSTIMER3_ARMV8_M_DEV               SYSTIMER3_ARMV8_M_DEV_S
+
+    #define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ    ( 25000000ul )
+    #define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ    ( 25000000ul )
+    #define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ    ( 25000000ul )
+    #define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ    ( 25000000ul )
+#endif /* ifdef RTE_TIMEOUT */
+
+/* CMSDK GPIO driver structures */
+#ifdef RTE_GPIO
+    #define GPIO0_CMSDK_S
+    #define GPIO0_CMSDK_DEV    GPIO0_CMSDK_DEV_S
+    #define GPIO1_CMSDK_S
+    #define GPIO1_CMSDK_DEV    GPIO1_CMSDK_DEV_S
+    #define GPIO2_CMSDK_S
+    #define GPIO2_CMSDK_DEV    GPIO2_CMSDK_DEV_S
+    #define GPIO3_CMSDK_S
+    #define GPIO3_CMSDK_DEV    GPIO3_CMSDK_DEV_S
+#endif
+
+/* System Watchdogs */
+#ifdef RTE_WATCHDOG
+    #define SYSWDOG_ARMV8_M_S
+    #define SYSWDOG_ARMV8_M_DEV    SYSWDOG_ARMV8_M_DEV_S
+#endif
+
+/* ARM MPC SIE 310 driver structures */
+#ifdef RTE_VM0_MPC
+    #define MPC_VM0_S
+    #define MPC_VM0_DEV    MPC_VM0_DEV_S
+#endif
+#ifdef RTE_VM1_MPC
+    #define MPC_VM1_S
+    #define MPC_VM1_DEV    MPC_VM1_DEV_S
+#endif
+#ifdef RTE_SSRAM2_MPC
+    #define MPC_SSRAM2_S
+    #define MPC_SSRAM2_DEV    MPC_SSRAM2_DEV_S
+#endif
+#ifdef RTE_SSRAM3_MPC
+    #define MPC_SSRAM3_S
+    #define MPC_SSRAM3_DEV    MPC_SSRAM3_DEV_S
+#endif
+
+/* ARM PPC driver structures */
+#define PPC_SSE300_MAIN0_S
+#define PPC_SSE300_MAIN0_DEV          PPC_SSE300_MAIN0_DEV_S
+#define PPC_SSE300_MAIN_EXP0_S
+#define PPC_SSE300_MAIN_EXP0_DEV      PPC_SSE300_MAIN_EXP0_DEV_S
+#define PPC_SSE300_MAIN_EXP1_S
+#define PPC_SSE300_MAIN_EXP1_DEV      PPC_SSE300_MAIN_EXP1_DEV_S
+#define PPC_SSE300_MAIN_EXP2_S
+#define PPC_SSE300_MAIN_EXP2_DEV      PPC_SSE300_MAIN_EXP2_DEV_S
+#define PPC_SSE300_MAIN_EXP3_S
+#define PPC_SSE300_MAIN_EXP3_DEV      PPC_SSE300_MAIN_EXP3_DEV_S
+#define PPC_SSE300_PERIPH0_S
+#define PPC_SSE300_PERIPH0_DEV        PPC_SSE300_PERIPH0_DEV_S
+#define PPC_SSE300_PERIPH1_S
+#define PPC_SSE300_PERIPH1_DEV        PPC_SSE300_PERIPH1_DEV_S
+#define PPC_SSE300_PERIPH_EXP0_S
+#define PPC_SSE300_PERIPH_EXP0_DEV    PPC_SSE300_PERIPH_EXP0_DEV_S
+#define PPC_SSE300_PERIPH_EXP1_S
+#define PPC_SSE300_PERIPH_EXP1_DEV    PPC_SSE300_PERIPH_EXP1_DEV_S
+#define PPC_SSE300_PERIPH_EXP2_S
+#define PPC_SSE300_PERIPH_EXP2_DEV    PPC_SSE300_PERIPH_EXP2_DEV_S
+#define PPC_SSE300_PERIPH_EXP3_S
+#define PPC_SSE300_PERIPH_EXP3_DEV    PPC_SSE300_PERIPH_EXP3_DEV_S
+
+/* ARM SPI PL022 */
+/* Invalid device stubs are not defined */
+#define DEFAULT_SPI_SPEED_HZ    4000000U /* 4MHz */
+#ifdef RTE_SPI1
+    #define SPI1_PL022_S
+    #define SPI1_PL022_DEV      SPI1_PL022_DEV_S
+#endif
+
+#endif /* __DEVICE_CFG_H__ */