Separate ML model from NS image

.github/workflows/build.yaml

@@ -26,8 +26,6 @@ jobs:
         audio: [ROM, VSI]
         inference: [ETHOS, SOFTWARE]
         exclude:
-          - application: speech-recognition
-            inference: SOFTWARE
           - application: object-detection
             audio: VSI
     steps:

.gitlab-ci.yml

@@ -329,7 +329,7 @@ sw-vsi-configs-test:
          TOOLCHAIN: [ARMCLANG]
        -
          << : *pipeline_config_corstone315
-         APP: [keyword-detection]
+         APP: [keyword-detection, speech-recognition]
          INFERENCE: [SOFTWARE]
          AUDIO: [ROM, VSI]
          TOOLCHAIN: [ARMCLANG]
@@ -347,7 +347,7 @@ sw-vsi-configs-test:
          TOOLCHAIN: [ARMCLANG]
        -
          << : *pipeline_config_corstone310
-         APP: [keyword-detection]
+         APP: [keyword-detection, speech-recognition]
          INFERENCE: [SOFTWARE]
          AUDIO: [ROM, VSI]
          TOOLCHAIN: [ARMCLANG]
@@ -359,7 +359,7 @@ sw-vsi-configs-test:
          TOOLCHAIN: [ARMCLANG]
        -
          << : *pipeline_config_corstone300
-         APP: [keyword-detection]
+         APP: [keyword-detection, speech-recognition]
          INFERENCE: [SOFTWARE]
          AUDIO: [ROM, VSI]
          TOOLCHAIN: [ARMCLANG]
@@ -382,16 +382,10 @@ gnu-toolchain-test:
     matrix:
        -
          << : *pipeline_config_corstone315
-         APP: [keyword-detection]
+         APP: [keyword-detection, speech-recognition]
          INFERENCE: [ETHOS, SOFTWARE]
          AUDIO: [ROM,VSI]
          TOOLCHAIN: [GNU]
-       -
-         << : *pipeline_config_corstone315
-         APP: [speech-recognition]
-         INFERENCE: [ETHOS]
-         AUDIO: [ROM,VSI]
-         TOOLCHAIN: [GNU]
        -
          << : *pipeline_config_corstone315
          APP: [object-detection]
@@ -400,28 +394,16 @@ gnu-toolchain-test:
          TOOLCHAIN: [GNU]
        -
          << : *pipeline_config_corstone310
-         APP: [keyword-detection]
+         APP: [keyword-detection, speech-recognition]
          INFERENCE: [ETHOS, SOFTWARE]
          AUDIO: [ROM,VSI]
          TOOLCHAIN: [GNU]
-       -
-         << : *pipeline_config_corstone310
-         APP: [speech-recognition]
-         INFERENCE: [ETHOS]
-         AUDIO: [ROM,VSI]
-         TOOLCHAIN: [GNU]
        -
          << : *pipeline_config_corstone300
-         APP: [keyword-detection]
+         APP: [keyword-detection, speech-recognition]
          INFERENCE: [ETHOS, SOFTWARE]
          AUDIO: [ROM,VSI]
          TOOLCHAIN: [GNU]
-       -
-         << : *pipeline_config_corstone300
-         APP: [speech-recognition]
-         INFERENCE: [ETHOS]
-         AUDIO: [ROM,VSI]
-         TOOLCHAIN: [GNU]
   variables:
     GIT_SUBMODULE_STRATEGY: recursive
 

applications/keyword_detection/CMakeLists.txt

@@ -183,6 +183,8 @@ iot_reference_arm_corstone3xx_tf_m_merge_images(
     keyword-detection
     ${NS_PROVISIONING_BUNDLE_LOAD_ADDRESS}
     ${CMAKE_BINARY_DIR}/helpers/provisioning/provisioning_data.bin
+    ${NS_DDR4_IMAGE_LOAD_ADDRESS}
+    ${SECTORS_BIN_DIR}/ddr.bin
 )
 
 iot_reference_arm_corstone3xx_generate_aws_update_digest_and_signature(

applications/object_detection/CMakeLists.txt

@@ -167,6 +167,8 @@ iot_reference_arm_corstone3xx_tf_m_merge_images(
     object-detection
     ${NS_PROVISIONING_BUNDLE_LOAD_ADDRESS}
     ${CMAKE_BINARY_DIR}/helpers/provisioning/provisioning_data.bin
+    ${NS_DDR4_IMAGE_LOAD_ADDRESS}
+    ${SECTORS_BIN_DIR}/ddr.bin
 )
 
 iot_reference_arm_corstone3xx_generate_aws_update_digest_and_signature(

applications/speech_recognition/CMakeLists.txt

@@ -194,6 +194,8 @@ iot_reference_arm_corstone3xx_tf_m_merge_images(
     speech-recognition
     ${NS_PROVISIONING_BUNDLE_LOAD_ADDRESS}
     ${CMAKE_BINARY_DIR}/helpers/provisioning/provisioning_data.bin
+    ${NS_DDR4_IMAGE_LOAD_ADDRESS}
+    ${SECTORS_BIN_DIR}/ddr.bin
 )
 
 iot_reference_arm_corstone3xx_generate_aws_update_digest_and_signature(

applications/speech_recognition/dsp/src/scheduler.cpp

@@ -200,7 +200,7 @@ uint32_t ulScheduler(
 
        // Add delay to allow some time for the connectivity task
        // to send and receive messages to and from the cloud.
-       vTaskDelay(100);
+       vTaskDelay(120);
     }
     *error=sdfError;
     return(nbSchedule);

bsp/CMakeLists.txt

@@ -48,6 +48,7 @@ if(ARM_CORSTONE_BSP_TARGET_PLATFORM STREQUAL "corstone300")
     set(NS_IMAGE_LOAD_ADDRESS 0x28040000 CACHE STRING "Non-secure user application loading address")
     set(S_PROVISIONING_BUNDLE_LOAD_ADDRESS 0x10022000 CACHE STRING "Secure provisioning bundle loading address")
     set(NS_PROVISIONING_BUNDLE_LOAD_ADDRESS 0x211FF000 CACHE STRING "Non-Secure provisioning bundle loading address")
+    set(NS_DDR4_IMAGE_LOAD_ADDRESS 0x60000000 CACHE STRING "Non-Secure Double Data Rate RAM image loading address")
 
     set(ETHOS_U_BASE_ADDR "0x48102000" CACHE STRING "Ethos-U NPU base address" FORCE)
     set(ETHOS_U_IRQN "56" CACHE STRING "Ethos-U NPU Interrupt" FORCE)
@@ -75,6 +76,7 @@ elseif(ARM_CORSTONE_BSP_TARGET_PLATFORM STREQUAL "corstone310")
     set(NS_IMAGE_LOAD_ADDRESS 0x28040000 CACHE STRING "Non-secure user application loading address")
     set(S_PROVISIONING_BUNDLE_LOAD_ADDRESS 0x11022000 CACHE STRING "Secure provisioning bundle loading address")
     set(NS_PROVISIONING_BUNDLE_LOAD_ADDRESS 0x213FF000 CACHE STRING "Non-Secure provisioning bundle loading address")
+    set(NS_DDR4_IMAGE_LOAD_ADDRESS 0x60000000 CACHE STRING "Non-Secure Double Data Rate RAM image loading address")
 
     set(ETHOS_U_BASE_ADDR "0x40004000" CACHE STRING "Ethos-U NPU base address" FORCE)
     set(ETHOS_U_IRQN "16" CACHE STRING "Ethos-U NPU Interrupt" FORCE)
@@ -104,6 +106,7 @@ elseif(ARM_CORSTONE_BSP_TARGET_PLATFORM STREQUAL "corstone315")
     set(S_CM_PROVISIONING_BUNDLE_LOAD_ADDRESS 0x12024000 CACHE STRING "Secure CM provisioning bundle loading address")
     set(S_DM_PROVISIONING_BUNDLE_LOAD_ADDRESS 0x1202aa00 CACHE STRING "Secure DM provisioning bundle loading address")
     set(NS_PROVISIONING_BUNDLE_LOAD_ADDRESS 0x213FF000 CACHE STRING "Non-Secure provisioning bundle loading address")
+    set(NS_DDR4_IMAGE_LOAD_ADDRESS 0x60000000 CACHE STRING "Non-Secure Double Data Rate RAM image loading address")
 
     set(ETHOS_U_BASE_ADDR "0x40004000" CACHE STRING "Ethos-U NPU base address" FORCE)
     set(ETHOS_U_IRQN "16" CACHE STRING "Ethos-U NPU Interrupt" FORCE)

bsp/corstone300/an552_ns.ld

@@ -1,4 +1,4 @@
-/* Copyright 2009-2023 Arm Limited and/or its affiliates
+/* Copyright 2009-2024 Arm Limited and/or its affiliates
  * <[email protected]>
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -104,9 +104,6 @@ SECTIONS
     LONG (LOADADDR(.data))
     LONG (ADDR(.data))
     LONG (SIZEOF(.data) / 4)
-    LONG (LOADADDR(.model))
-    LONG (ADDR(.model))
-    LONG (SIZEOF(.model) / 4)
     __copy_table_end__ = .;
 
     /* .zero.table */
@@ -192,7 +189,7 @@ SECTIONS
 
   } > RAM
 
-  .model : AT ( LOADADDR(.data) + SIZEOF(.data) )
+  ddr.bin :
   {
     __ddr_start__ = .;
     . = ALIGN(16);
@@ -204,30 +201,16 @@ SECTIONS
     . = ALIGN (16);
     /* labels */
     *(labels)
-    __ddr_end__ = .;
-  } > DDR
-
-  __ddr_load_address__ = LOADADDR(.model);
-
-  .activationbuf :
-  {
     . = ALIGN (16);
     *(.bss.NoInit.activation_buf_sram)
     *(.bss.NoInit.activation_buf_dram)
-  } > DDR AT > DDR
-
-  .vsibuffer :
-  {
     . = ALIGN (4);
     /* Buffer for transferring VSI audio data from S to NS */
     *(.bss.NoInit.vsi_audio_buffer)
-  } > DDR AT > DDR
-
-  .ethosucache :
-  {
     . = ALIGN (16);
     *(.bss.NoInit.ethos_u_cache)
-  } > DDR AT > DDR
+    __ddr_end__ = .;
+  } > DDR
 
   .bss :
   {

bsp/corstone300/an552_ns.sct

@@ -1,32 +1,64 @@
-/* Copyright 2023-2024, Arm Limited and/or its affiliates
- * <[email protected]>
- * SPDX-License-Identifier: Apache-2.0
+#! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main+mve.fp+fp.dp -E -x c
+/*
+ * Copyright (c) 2023-2024, Arm Limited. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  */
 
-LR_CODE (0x28000000 + ((((0) + (0x40000)) + (0x400)))) {
-    ER_CODE (0x28000000 + ((((0) + (0x40000)) + (0x400)))) (((0x340000) - (0x400) - (0xC00))) {
+#define FLASH_NS_PARTITION_SIZE 0x340000
+#define FLASH_S_PARTITION_SIZE  0x40000
+#define ROM_START               0x28000000
+#define BL2_HEADER_SIZE         0x400
+#define BL2_TRAILER_SIZE        0xC00
+#define ISRAM0_BASE_ADDRESS     0x21000000
+#define ISRAM0_S_SIZE           0x00020000
+#define ISRAM0_SIZE             0x00100000
+#define ISRAM1_SIZE             0x00100000
+#define PROVISIONING_SIZE       0x1000
+#define STACK_SIZE              0x00001000
+#define HEAP_SIZE               0x000C0000
+
+LOAD_REGION_0 (ROM_START + ((((0) + (FLASH_S_PARTITION_SIZE)) + (BL2_HEADER_SIZE))))
+{
+    flash.bin (ROM_START + ((((0) + (FLASH_S_PARTITION_SIZE)) + (BL2_HEADER_SIZE)))) (((FLASH_NS_PARTITION_SIZE) - (BL2_HEADER_SIZE) - (BL2_TRAILER_SIZE))) {
         *.o (RESET +First)
         * (InRoot$$Sections)
         * (+RO)
     }
 
-    /* Where 0x20000 is NS_RAM_SIZE and 0x1000 is the provisioning size */
-    ER_DATA (0x21000000 + 0x20000) (0x00200000 - 0x20000 - 0x1000) {
+    ; The last 0x1000 bytes are reserved for the provisioning bundle
+    data.bin (ISRAM0_BASE_ADDRESS + ISRAM0_S_SIZE) ((ISRAM0_SIZE -ISRAM0_S_SIZE) + ISRAM1_SIZE - PROVISIONING_SIZE) {
         * (+ZI +RW)
     }
 
-    ARM_LIB_STACK +0 ALIGN 32 EMPTY (0x0001000) {
+    ARM_LIB_STACK +0 ALIGN 32 EMPTY (STACK_SIZE) {
     }
-    ARM_LIB_HEAP +0 ALIGN 8 EMPTY (0x00C0000) {
+    ARM_LIB_HEAP +0 ALIGN 8 EMPTY (HEAP_SIZE) {
     }
+}
 
+;---------------------------------------------------------
+; Second load region (DDR)
+;---------------------------------------------------------
+LOAD_REGION_1       0x60000000                   0x10000000
+{
     ;-----------------------------------------------------
-    ; SSE-300's internal SRAM of 4MiB - reserved for
-    ; activation buffers.
-    ; This region should have 3 cycle read latency from
-    ; both Cortex-M55 and Ethos-U55
+    ; 32 MiB of DDR space for neural network model,
+    ; input vectors and labels. If the activation buffer
+    ; size required by the network is bigger than the
+    ; SRAM size available, it is accommodated here.
     ;-----------------------------------------------------
-    ddr.bin       0x60000000  NOCOMPRESS ALIGN 16 0x10000000
+    ddr.bin         0x60000000 NOCOMPRESS ALIGN 16 0x10000000
     {
         ; nn model's baked in input matrices
         *.o (ifm)
@@ -37,19 +69,16 @@ LR_CODE (0x28000000 + ((((0) + (0x40000)) + (0x400)))) {
         ; labels
         *.o (labels)
 
-        ; if the activation buffer (tensor arena) doesn't
-        ; fit in the SRAM region, we accommodate it here
-        *.o (activation_buf)
-
-        ; activation buffers a.k.a tensor arena when memory mode dedicated sram
-        *.o (.bss.NoInit.activation_buf_dram)
-
         ; activation buffers a.k.a tensor arena when
         ; memory mode sram only or shared sram
         *.o (.bss.NoInit.activation_buf_sram)
 
+        ; activation buffers a.k.a tensor arena when memory mode dedicated sram
+        *.o (.bss.NoInit.activation_buf_dram)
+
         ; Buffer for transferring VSI audio data from S to NS
         *.o (.bss.NoInit.vsi_audio_buffer)
+
         ; Cache area (if used)
         *.o (.bss.NoInit.ethos_u_cache)
     }

bsp/corstone310/an555_ns.ld

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2009-2024 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -118,9 +118,6 @@ SECTIONS
     LONG (LOADADDR(.data))
     LONG (ADDR(.data))
     LONG (SIZEOF(.data) / 4)
-    LONG (LOADADDR(.model))
-    LONG (ADDR(.model))
-    LONG (SIZEOF(.model) / 4)
     __copy_table_end__ = .;
 
     /* .zero.table */
@@ -206,7 +203,7 @@ SECTIONS
 
   } > RAM
 
-  .model : AT ( LOADADDR(.data) + SIZEOF(.data) )
+  ddr.bin :
   {
     __ddr_start__ = .;
     . = ALIGN(16);
@@ -218,30 +215,16 @@ SECTIONS
     . = ALIGN (16);
     /* labels */
     *(labels)
-    __ddr_end__ = .;
-  } > DDR
-
-  __ddr_load_address__ = LOADADDR(.model);
-
-  .activationbuf :
-  {
     . = ALIGN (16);
     *(.bss.NoInit.activation_buf_sram)
     *(.bss.NoInit.activation_buf_dram)
-  } > DDR AT > DDR
-
-  .vsibuffer :
-  {
     . = ALIGN (4);
     /* Buffer for transferring VSI audio data from S to NS */
     *(.bss.NoInit.vsi_audio_buffer)
-  } > DDR AT > DDR
-
-  .ethosucache :
-  {
     . = ALIGN (16);
     *(.bss.NoInit.ethos_u_cache)
-  } > DDR AT > DDR
+    __ddr_end__ = .;
+  } > DDR
 
   .bss :
   {