reorganise project

interfaces/WISHBONE_IF.sv → include/interfaces/WISHBONE_IF.sv

@@ -1,12 +1,12 @@
 /**
  * @file WISHBONE_IF.sv
  * @author Jacob Chisholm (https://Jchisholm204.github.io)
- * @brief 
+ * @brief
  * @version 0.1
  * @date Created: 2025-05-31
  * @modified Last Modified: 2025-05-31
  *
- * 
+ *
  * All wishbone signals must be active high
  * Port sizes must be 8, 16, 32, or 64 bit
  *  Default port size is 32 bit

processor/Processor.sv

@@ -10,9 +10,9 @@
  */
 
 `timescale 1ns/100ps
-`include "pipeline_types.svh"
-`include "reg_transport.svh"
-`include "rv32_isa.svh"
+// `include "pipeline_types.svh"
+// `include "reg_transport.svh"
+// `include "rv32_isa.svh"
 import pipeline_types::*;
 import reg_transport::reg_transport_t;
 import rv32_isa::*;

processor/memory/RegisterFile.sv

@@ -25,9 +25,9 @@ module RegisterFile #(
     input logic [addr_width-1:0] iAddrRs1,
     input logic [addr_width-1:0] iAddrRs2,
     output logic [reg_width-1:0] oRs1,
-    output logic [reg_width-1:0] oRs2,
+    output logic [reg_width-1:0] oRs2
     `ifndef RF_TOP
-    BBUS_IF.slave dbg_acc
+    ,BBUS_IF.slave dbg_acc
     `endif
 );
 

pytest.ini

@@ -1,2 +1,3 @@
 [pytest]
 python_files = test_*.py
+pythonpath="sim"

processor/sim/.gitignore → sim/.gitignore

@@ -1,3 +1,5 @@
 results.xml/*
 sim_build/*
 __pycache__/*
+.pytest_cache/*
+*/__pycache__/*

processor/sim/debug_types.py → sim/incl/debug_types.py

@@ -1,4 +1,4 @@
-from SuperStruct import SuperStruct
+from incl.SuperStruct import SuperStruct
 from cocotb.handle import ModifiableObject
 
 

processor/sim/pipeline_types.py → sim/incl/pipeline_types.py

@@ -1,6 +1,6 @@
-from SuperStruct import SuperStruct
+from incl.SuperStruct import SuperStruct
 from cocotb.handle import ModifiableObject
-from reg_transport_t import reg_transport_t
+from incl.reg_transport_t import reg_transport_t
 
 
 class pipe_control_t(SuperStruct):

processor/sim/reg_transport_t.py → sim/incl/reg_transport_t.py

@@ -1,5 +1,5 @@
 from cocotb.handle import ModifiableObject
-from SuperStruct import SuperStruct
+from incl.SuperStruct import SuperStruct
 
 
 class reg_transport_t(SuperStruct):

sim/pyproject.toml

@@ -0,0 +1,3 @@
+[tool.pytest.ini_options]
+pythonpath = "."
+

processor/sim/test_alu.py → sim/test_alu.py

@@ -5,9 +5,9 @@
 from cocotb.runner import get_runner
 from pathlib import Path
 import rv32_isa
-import test_shift
-import testbench
-import sources
+import test_alu_shift as test_shift
+import util.testbench as testbench
+from util.sources import Sources
 
 
 @cocotb.test()
@@ -121,10 +121,14 @@ async def alu_rem_test(dut):
 
 def test_alu_runner():
     tb = testbench.TB("test_alu", "ALU")
-    tb.add_sources(sources.ISA_SOURCES)
-    tb.add_sources(sources.ALU_SOURCES)
+    tb.add_sources(Sources.ISA())
+    tb.add_sources(Sources.TYPES())
+    tb.add_sources(Sources.INTERFACES())
+    tb.add_sources(Sources.PROC())
+    tb.add_sources(Sources.ALU())
+    print(tb.sources)
     tb.run_tests()
 
 
-if __name__ == "main":
+if __name__ == "__main__":
     test_alu_runner()

processor/sim/test_bitwise.py → sim/test_alu_bitwise.py

@@ -4,13 +4,8 @@
 from cocotb.triggers import Timer
 from cocotb.runner import get_runner
 from pathlib import Path
-
-
-def to_signed32(n):
-    """Convert unsigned 32-bit int to signed 32-bit."""
-    n = n & 0xFFFFFFFF
-    return n if n < 0x80000000 else n - 0x100000000
-
+from util.representation import to_signed32 as to_signed32
+import util.testbench as testbench
 
 @cocotb.test()
 async def and_test_specific(dut):
@@ -118,33 +113,8 @@ async def xor_test_random(dut):
 
 
 def test_bitwise_runner():
-    sim = os.getenv("SIM", "icarus")
-
-    proj_path = Path(__file__).resolve().parent.parent
-
-    sources = [proj_path / "ALU/BitWise.sv"]
-
-    if sim == "icarus":
-        build_args = ["-DICARUS_TRACE_ARRAYS", "-DICARUS_FST"]
-    else:
-        build_args = ["--trace", "-Wno-fatal"]
-
-    runner = get_runner(sim)
-    runner.build(
-        verilog_sources=sources,
-        hdl_toplevel="BitWise",
-        clean=False,
-        waves=True,
-        # build_args=["-DICARUS_TRACE_ARRAYS", "-DICARUS_FST"],
-        build_args=build_args,
-        always=True,
-    )
-    runner.test(
-        hdl_toplevel="BitWise",
-        test_module="test_bitwise",
-        plusargs=["-fst"],
-        waves=True
-    )
+    tb = testbench.TB("test_alu_bitwise", "BitWise")
+    tb.add_source("processor/ALU/BitWise.sv")
 
 
 if __name__ == "__main__":

processor/sim/test_cla.py → sim/test_alu_cla.py

@@ -4,6 +4,7 @@
 from cocotb.triggers import Timer
 from cocotb.runner import get_runner
 from pathlib import Path
+import util.testbench as testbench
 
 
 @cocotb.test()
@@ -50,33 +51,8 @@ async def cla_add_tests(dut):
 
 
 def test_cla_runner():
-    sim = os.getenv("SIM", "icarus")
-
-    proj_path = Path(__file__).resolve().parent.parent
-
-    sources = [proj_path / "ALU/CLA.sv"]
-
-    if sim == "icarus":
-        build_args = ["-DICARUS_TRACE_ARRAYS", "-DICARUS_FST"]
-    else:
-        build_args = ["--trace", "-Wno-fatal"]
-
-    runner = get_runner(sim)
-    runner.build(
-        verilog_sources=sources,
-        hdl_toplevel="CLA",
-        clean=False,
-        waves=True,
-        # build_args=["-DICARUS_TRACE_ARRAYS", "-DICARUS_FST"],
-        build_args=build_args,
-        always=True,
-    )
-    runner.test(
-        hdl_toplevel="CLA",
-        test_module="test_cla",
-        plusargs=["-fst"],
-        waves=True
-    )
+    tb = testbench.TB("test_alu_cla", "CLA")
+    tb.add_source("processor/ALU/CLA.sv")
 
 
 if __name__ == "__main__":

processor/sim/test_divisor.py → sim/test_alu_divisor.py

@@ -4,6 +4,7 @@
 from cocotb.triggers import Timer
 from cocotb.runner import get_runner
 from pathlib import Path
+import util.testbench as testbench
 
 
 @cocotb.test()
@@ -94,32 +95,8 @@ async def div32_small(dut):
 
 
 def test_div32_runner():
-    sim = os.getenv("SIM", "icarus")
-
-    proj_path = Path(__file__).resolve().parent.parent
-
-    sources = [proj_path / "ALU/DIV32.sv"]
-
-    if sim == "icarus":
-        build_args = ["-DICARUS_TRACE_ARRAYS", "-DICARUS_FST"]
-    else:
-        build_args = ["--trace", "-Wno-fatal"]
-
-    runner = get_runner(sim)
-    runner.build(
-        verilog_sources=sources,
-        hdl_toplevel="DIV32",
-        clean=False,
-        waves=True,
-        build_args=build_args,
-        always=True,
-    )
-    runner.test(
-        hdl_toplevel="DIV32",
-        test_module="test_divisor",
-        plusargs=["-fst"],
-        waves=True
-    )
+    tb = testbench.TB("test_alu_divisor", "DIV32")
+    tb.add_source("processor/ALU/DIV32.sv")
 
 
 if __name__ == "__main__":

processor/sim/test_shift.py → sim/test_alu_shift.py

@@ -1,7 +1,7 @@
 import cocotb
 import random
 from cocotb.triggers import Timer
-import testbench
+import util.testbench as testbench
 
 
 def to_signed32(n):
@@ -94,8 +94,8 @@ async def left_logic_test(dut):
 
 
 def test_shift_runner():
-    tb = testbench.TB("test_shift", "SHIFT")
-    tb.add_source("ALU/SHIFT.sv")
+    tb = testbench.TB("test_alu_shift", "SHIFT")
+    tb.add_source("processor/ALU/SHIFT.sv")
     tb.run_tests()