UART

uart protocol implementation in systemverilog using 2 process fsm style

stuff i figured out

• as soon as the high line becomes low we count till half the start bit period and uske baad we reset and count 1 bit period this causes us to sample the value at the midpoint of every bit

• stop bit is important as it gives the reciever a while to prepare for the next dataframe also a question that i always had was how does the reciever figure out it was a stop bit or a data bit basically as both the tx and rx know the packet format the reciever counts the no of btis it has got and then checks for stop bit if the stop bit is say 0 it indicates a framing error

protocol

UART data packet

• A start bit indicates start of packet

  • The default HIGH level is pulled down to LOW for one clock cycle
  • The receiving UART detects the transition and start's counting till half the baud period and then resets and prepares to read the subsequent bits in intervals of baud period this allows to sample all the bits at the center

• The data frame holds the actual data. It can be 5 to 8 bits long if the parity bit is used, or 9 bits long if parity is not used.

  • LSB first

• Parity bit is used to check for errors. It can follow odd or even parity.

• Stop bit indicates end of packet

  • The signal is pulled HIGH for 1 to 2 cycles.

State machines

Transmitter state machine	Receiver state machine

port interfaces

• for transmitter,

Name of port	function
data	input data bus to be sent
send_en	enable signal to start sending
clk	clk to the modules
next_d_ready	signal indicating whether next data packet can be sent
tx_op	1 bit data to be sent

• for reciever,

Name of port	function
rx_b	bit recieved
recieved_data	the bus of data that is recieved
clk	input data to be sent
ready_recieve	signal indicating the reciever is ready to recieve

credits and references

1. Analog Devices
2. NandLand implementation
3. https://github.com/Ashwin-Rajesh/Verilog_comm