Clock

This is my implementation of a clock in vhdl; intended for the TCL interface I co-authored with my Dad (@philipabbey). ℹ️

Around 15 hours 35 mins to write the code and make a write up.

Running

First compile for Modelsim:

.\modelsim_compile.cmd

Then load Modelsim:

.\modelsim.cmd

Then click the vis button at the end of the top-left toolbar.
You will be greeted by a new window that has some controls, click autostep.
Time will begin to advance. At any time you can disable autostep and step through manually using the step button.
To reload the simulation, press restart.
When autostep is disabled you can click goto cursor to view what the display looks like where your cursor is in the waveform.
You can enable and disable 24 hour mode with the checkbox.
You can switch modes using the radio buttons.
You can interact with the silence, up, down and ok buttons.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
.vscode		.vscode
media		media
Clock Project.pptx		Clock Project.pptx
LICENCE		LICENCE
README.md		README.md
constraints.xdc		constraints.xdc
modelsim.cmd		modelsim.cmd
modelsim_compile.cmd		modelsim_compile.cmd
nice_time.vhdl		nice_time.vhdl
setup.tcl		setup.tcl
sevseg_decode.vhdl		sevseg_decode.vhdl
sevseg_display.tcl		sevseg_display.tcl
sevseg_pkg.vhdl		sevseg_pkg.vhdl
test_time_display.vhdl		test_time_display.vhdl
time_display.vhdl		time_display.vhdl
time_display_pkg.vhdl		time_display_pkg.vhdl
vhdl_ls.toml		vhdl_ls.toml
wave.do		wave.do