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add support for SPV_INTEL_subgroup_buffer_prefetch #442

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merged 2 commits into from
Aug 28, 2024
Merged

add support for SPV_INTEL_subgroup_buffer_prefetch #442

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63ad152
add support for SPV_INTEL_subgroup_buffer_prefetch
bashbaug Aug 1, 2024
ca65b91
add optional memory operands operand
bashbaug Aug 22, 2024
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2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.bf
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Original file line number Diff line number Diff line change
Expand Up @@ -1263,6 +1263,7 @@ namespace Spv
FPGAArgumentInterfacesINTEL = 6174,
GlobalVariableHostAccessINTEL = 6187,
GlobalVariableFPGADecorationsINTEL = 6189,
SubgroupBufferPrefetchINTEL = 6220,
GroupUniformArithmeticKHR = 6400,
MaskedGatherScatterINTEL = 6427,
CacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2219,6 +2220,7 @@ namespace Spv
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
18 changes: 18 additions & 0 deletions include/spirv/unified1/spirv.core.grammar.json
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Expand Up @@ -9920,6 +9920,18 @@
"capabilities" : [ "SplitBarrierINTEL" ],
"version" : "None"
},
{
"opname" : "OpSubgroupBlockPrefetchINTEL",
"class" : "Group",
"opcode" : 6221,
"operands" : [
{ "kind" : "IdRef", "name" : "'Ptr'" },
{ "kind" : "IdRef", "name" : "'NumBytes'" },
{ "kind" : "MemoryAccess", "quantifier" : "?" }
],
"capabilities" : [ "SubgroupBufferPrefetchINTEL" ],
"version" : "None"
},
{
"opname" : "OpGroupIMulKHR",
"class" : "Group",
Expand Down Expand Up @@ -16738,6 +16750,12 @@
"extensions": [ "SPV_INTEL_global_variable_fpga_decorations" ],
"version" : "None"
},
{
"enumerant" : "SubgroupBufferPrefetchINTEL",
"value" : 6220,
"extensions": [ "SPV_INTEL_subgroup_buffer_prefetch" ],
"version" : "None"
},
{
"enumerant" : "GroupUniformArithmeticKHR",
"value" : 6400,
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.cs
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Expand Up @@ -1262,6 +1262,7 @@ public enum Capability
FPGAArgumentInterfacesINTEL = 6174,
GlobalVariableHostAccessINTEL = 6187,
GlobalVariableFPGADecorationsINTEL = 6189,
SubgroupBufferPrefetchINTEL = 6220,
GroupUniformArithmeticKHR = 6400,
MaskedGatherScatterINTEL = 6427,
CacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2218,6 +2219,7 @@ public enum Op
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1233,6 +1233,7 @@ typedef enum SpvCapability_ {
SpvCapabilityFPGAArgumentInterfacesINTEL = 6174,
SpvCapabilityGlobalVariableHostAccessINTEL = 6187,
SpvCapabilityGlobalVariableFPGADecorationsINTEL = 6189,
SpvCapabilitySubgroupBufferPrefetchINTEL = 6220,
SpvCapabilityGroupUniformArithmeticKHR = 6400,
SpvCapabilityMaskedGatherScatterINTEL = 6427,
SpvCapabilityCacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2164,6 +2165,7 @@ typedef enum SpvOp_ {
SpvOpConvertBF16ToFINTEL = 6117,
SpvOpControlBarrierArriveINTEL = 6142,
SpvOpControlBarrierWaitINTEL = 6143,
SpvOpSubgroupBlockPrefetchINTEL = 6221,
SpvOpGroupIMulKHR = 6401,
SpvOpGroupFMulKHR = 6402,
SpvOpGroupBitwiseAndKHR = 6403,
Expand Down Expand Up @@ -2909,6 +2911,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy
case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
Expand Down Expand Up @@ -3826,6 +3829,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) {
case SpvCapabilityFPGAArgumentInterfacesINTEL: return "FPGAArgumentInterfacesINTEL";
case SpvCapabilityGlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
case SpvCapabilityGlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
case SpvCapabilitySubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
case SpvCapabilityCacheControlsINTEL: return "CacheControlsINTEL";
Expand Down Expand Up @@ -4703,6 +4707,7 @@ inline const char* SpvOpToString(SpvOp value) {
case SpvOpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
case SpvOpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case SpvOpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
case SpvOpGroupIMulKHR: return "OpGroupIMulKHR";
case SpvOpGroupFMulKHR: return "OpGroupFMulKHR";
case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1229,6 +1229,7 @@ enum Capability {
CapabilityFPGAArgumentInterfacesINTEL = 6174,
CapabilityGlobalVariableHostAccessINTEL = 6187,
CapabilityGlobalVariableFPGADecorationsINTEL = 6189,
CapabilitySubgroupBufferPrefetchINTEL = 6220,
CapabilityGroupUniformArithmeticKHR = 6400,
CapabilityMaskedGatherScatterINTEL = 6427,
CapabilityCacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2160,6 +2161,7 @@ enum Op {
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down Expand Up @@ -2905,6 +2907,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
Expand Down Expand Up @@ -3822,6 +3825,7 @@ inline const char* CapabilityToString(Capability value) {
case CapabilityFPGAArgumentInterfacesINTEL: return "FPGAArgumentInterfacesINTEL";
case CapabilityGlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
case CapabilityGlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
case CapabilitySubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
case CapabilityCacheControlsINTEL: return "CacheControlsINTEL";
Expand Down Expand Up @@ -4699,6 +4703,7 @@ inline const char* OpToString(Op value) {
case OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
case OpGroupIMulKHR: return "OpGroupIMulKHR";
case OpGroupFMulKHR: return "OpGroupFMulKHR";
case OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
Expand Down
5 changes: 5 additions & 0 deletions include/spirv/unified1/spirv.hpp11
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Expand Up @@ -1229,6 +1229,7 @@ enum class Capability : unsigned {
FPGAArgumentInterfacesINTEL = 6174,
GlobalVariableHostAccessINTEL = 6187,
GlobalVariableFPGADecorationsINTEL = 6189,
SubgroupBufferPrefetchINTEL = 6220,
GroupUniformArithmeticKHR = 6400,
MaskedGatherScatterINTEL = 6427,
CacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2160,6 +2161,7 @@ enum class Op : unsigned {
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down Expand Up @@ -2905,6 +2907,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) {
case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break;
case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpSubgroupBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break;
case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break;
case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break;
Expand Down Expand Up @@ -3822,6 +3825,7 @@ inline const char* CapabilityToString(Capability value) {
case CapabilityFPGAArgumentInterfacesINTEL: return "FPGAArgumentInterfacesINTEL";
case CapabilityGlobalVariableHostAccessINTEL: return "GlobalVariableHostAccessINTEL";
case CapabilityGlobalVariableFPGADecorationsINTEL: return "GlobalVariableFPGADecorationsINTEL";
case CapabilitySubgroupBufferPrefetchINTEL: return "SubgroupBufferPrefetchINTEL";
case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR";
case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL";
case CapabilityCacheControlsINTEL: return "CacheControlsINTEL";
Expand Down Expand Up @@ -4699,6 +4703,7 @@ inline const char* OpToString(Op value) {
case OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL";
case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL";
case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL";
case OpSubgroupBlockPrefetchINTEL: return "OpSubgroupBlockPrefetchINTEL";
case OpGroupIMulKHR: return "OpGroupIMulKHR";
case OpGroupFMulKHR: return "OpGroupFMulKHR";
case OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.json
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Expand Up @@ -1206,6 +1206,7 @@
"FPGAArgumentInterfacesINTEL": 6174,
"GlobalVariableHostAccessINTEL": 6187,
"GlobalVariableFPGADecorationsINTEL": 6189,
"SubgroupBufferPrefetchINTEL": 6220,
"GroupUniformArithmeticKHR": 6400,
"MaskedGatherScatterINTEL": 6427,
"CacheControlsINTEL": 6441,
Expand Down Expand Up @@ -2162,6 +2163,7 @@
"OpConvertBF16ToFINTEL": 6117,
"OpControlBarrierArriveINTEL": 6142,
"OpControlBarrierWaitINTEL": 6143,
"OpSubgroupBlockPrefetchINTEL": 6221,
"OpGroupIMulKHR": 6401,
"OpGroupFMulKHR": 6402,
"OpGroupBitwiseAndKHR": 6403,
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.lua
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Expand Up @@ -1220,6 +1220,7 @@ spv = {
FPGAArgumentInterfacesINTEL = 6174,
GlobalVariableHostAccessINTEL = 6187,
GlobalVariableFPGADecorationsINTEL = 6189,
SubgroupBufferPrefetchINTEL = 6220,
GroupUniformArithmeticKHR = 6400,
MaskedGatherScatterINTEL = 6427,
CacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2151,6 +2152,7 @@ spv = {
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spirv.py
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Expand Up @@ -1191,6 +1191,7 @@
'FPGAArgumentInterfacesINTEL' : 6174,
'GlobalVariableHostAccessINTEL' : 6187,
'GlobalVariableFPGADecorationsINTEL' : 6189,
'SubgroupBufferPrefetchINTEL' : 6220,
'GroupUniformArithmeticKHR' : 6400,
'MaskedGatherScatterINTEL' : 6427,
'CacheControlsINTEL' : 6441,
Expand Down Expand Up @@ -2101,6 +2102,7 @@
'OpConvertBF16ToFINTEL' : 6117,
'OpControlBarrierArriveINTEL' : 6142,
'OpControlBarrierWaitINTEL' : 6143,
'OpSubgroupBlockPrefetchINTEL' : 6221,
'OpGroupIMulKHR' : 6401,
'OpGroupFMulKHR' : 6402,
'OpGroupBitwiseAndKHR' : 6403,
Expand Down
2 changes: 2 additions & 0 deletions include/spirv/unified1/spv.d
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Expand Up @@ -1265,6 +1265,7 @@ enum Capability : uint
FPGAArgumentInterfacesINTEL = 6174,
GlobalVariableHostAccessINTEL = 6187,
GlobalVariableFPGADecorationsINTEL = 6189,
SubgroupBufferPrefetchINTEL = 6220,
GroupUniformArithmeticKHR = 6400,
MaskedGatherScatterINTEL = 6427,
CacheControlsINTEL = 6441,
Expand Down Expand Up @@ -2221,6 +2222,7 @@ enum Op : uint
OpConvertBF16ToFINTEL = 6117,
OpControlBarrierArriveINTEL = 6142,
OpControlBarrierWaitINTEL = 6143,
OpSubgroupBlockPrefetchINTEL = 6221,
OpGroupIMulKHR = 6401,
OpGroupFMulKHR = 6402,
OpGroupBitwiseAndKHR = 6403,
Expand Down