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MIPS-Architecture-CPU-design

BUAA SCSE - Computer Organization - Pipeline CPU design

implement effective data forward, and reduce unnecessary block in CPU

P3 is a single-cycle CPU drawn in logisim, with about 30 instructions.

P4 is a Verilog version of P3.

P5 is a basic pipeline CPU with about 10 instructions.

P6 with over 50 instructions .

P7 is a final version with some data exchange with device and error solutions.

You can coding in Mars, a MIPS interpreter, then generate instructions of your code, and run them in CPU.

MagicMars is a tool to show the MIPS interpreting result and you can compare it with output information in P4/P5/P6/P7.

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BUAA SCSE - Computer Organization - Pipeline CPU design

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