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IPC sensitivity to cache line size
Alexandr edited this page Apr 4, 2018
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This page is maintained by Alexandr Misevich
What is cache line size, what are expected effects and drawbacks?
What cache do we study, what trace do we use? How can one reproduce your results?
Provide table and performance You may also do one more study, varying cache miss latency as well
Your summary on your study
MIPT-V / MIPT-MIPS — Cycle-accurate pre-silicon simulation.