Supported MIPS instructions

Unfortunately, MIPT-MIPS supports reduced subset of MIPS instructions at the moment.

The list of unsupported instructions goes first as it may be more important. If instruction is not listed as supported or unsupported, it is not supported.

Unsupported Instructions

System call and CP0 (#122)

• syscall
• break
• sdbbp
• mtc0
• mfc0
• eret

MIPS IV Prefetches (#235)

• pref

Cache control

• cache
• sync
• synci

Partially supported instructions

Double word arithmetic instructions (#214)

No proper testing was performed, please report bugs if found

• dadd
• daddi
• daddiu
• daddu
• dclo
• dclz
• ddiv
• ddivu
• dmult
• dmultu
• dsll
• dsllv
• dsll32
• dsra
• dsra32
• dsrav
• dsrl
• dsrl32
• dsrlv
• dsub
• dsubu

Double word memory instructions (#215)

No proper testing was performed, please report bugs if found

• ld
• ldl
• ldr
• lld
• lwu
• scd
• sd
• sdl
• sdr

MIPS II conditional traps (#130)

These instructions don't cause actual traps now, they print a message to the screen

• teq
• teqi
• tge
• tgei
• tgeiu
• tgeu
• tlt
• tlti
• tltiu
• tltu
• tne
• tnei

MIPS II likely branches (#91)

These branches operate as usual branches, but they don't provide any hint to BPU

• beql
• bgezl
• bgezall
• bgtzl
• blezl
• bltzl
• bltzall
• bnel

Atomic operations

No atomicity warranty provided

• ll
• sc

Supported Instructions

• add
• addi
• addiu
• addu
• and
• andi
• beq
• bgez
• bgezal
• bgtz
• blez
• bltz
• bltzal
• bne
• clo
• clz
• div
• divu
• j
• jal
• jalr
• jr
• lb
• lbu
• lh
• lhu
• lui
• lw
• lwl
• lwr
• madd
• maddu
• mfhi
• mflo
• movn
• movz
• msub
• msubu
• mthi
• mtlo
• mul
• mult
• multu
• nor
• or
• ori
• sb
• sh
• sll
• sllv
• slt
• slti
• sltiu
• sltu
• sra
• srav
• srl
• srlv
• sub
• subu
• sw
• swl
• swr
• xor
• xori