PALANG is a logic resimulation tool accelerated by GPGPU developed by the research team Seyed Mani Sadati and Mohammad Shahidzade supervised by Prf. Behnam Ghavami at Shahid Bahonar University of kerman (SBUK) and first place of ICCAD-Contest 2020 problem C. PALANG is the best open-source tool for logic resimulation based on GPU which is parallelized by 2 dimensions. In particular, our tool solves a problem in the industry, which is described in the following link:
- Yanqing Zhang, Haoxing (Mark) Ren, Ben Keller, Brucek Khailany (NVIDIA) "GPU Accelerated Logic Re-simulation"
PALANG is developed based on the paper below but it has some diffrences and innovations:
- Stefan Holst, Michael E. Imhof and Hans-Joachim Wunderlich "High-Throughput Logic Timing Simulation on GPGPUs"
(PALANG supports ICCAD2020 benchmarks). This version of code is consistent with the one submitted to contest. So it may have some issues with your designs. If you faced any problems ask us in the issues!
Step 1: Download the source code. For example,
$ git clone https://github.com/ManiSadati/GPU_Logic_resimulator.gitStep 2: Go to the project root and build by
$ cd simulator1
$ make pre
$ make gpuNote that this will generate two binary files named preprocess and GPUsimulator.
- GNU Make (version >= 4.1)
- nvidia-cuda-toolkit (nvcc compiler) (version >= 5)
- CUDA-enabled GPU (cuda compute capability >= 7)
Note that it might work on lower dependencies.
This version of the code also doesn't work for GPU cards with less than 16GB memory (but in the next version we will support GPUs with lower memories).
Go to the simulator1 directory and run the binary preprocess with a sample case sample_test in the Test directory:
$ cd simulator1
$ ./preprocess ../test/sample_test.gv ../test/sample_test.sdf ../GENERIC_STD_CELL.vlib sample_test.gv is a gate level netlist description of the design.
sample_test.sdf is an SDF file that describes the delays of each gate in the design
GENERIC_STD_CELL.vlib is a standard cell library file, which describes the behavior of each standard cell gate in the design.
(Right now we only support limited combinatoinal gates that are described in the GENERIC_STD_CELL.vlib, but you can add any sequential gates to the library.)
This will make a file named netlist.txt which contains important informations about those files for the gpu-simulation part.
Here is the part that we run the simulation.
Go to the simulator1 directory and run the binary GPUsimulator with a sample case sample_test in the Test directory:
$ cd simulator1
$ ./GPUsimulator ../test/sample_test.vcd 0 100 sample_test.saif sample_test.vcd is a VCD file contains waveforms of the primary and pseudo-primary inputs ofthe design for the duration of the testbench.
after that there is 3 numbers. The first 2 are saif_start_time saif_end_time. That means it should simulate the design's waveforms during this period (0ps and 100ps).
sample_test.saif can be the name of the output file you want. It gives A SAIF file as an output (right now this version doesn't support vcd output).
Copyright (c) 2020, ManiSadati, MohammadShahidzade All rights reserved.
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