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My implementation of a UART RX/TX module in SystemVerilog.

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Name		Name	Last commit message	Last commit date
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src		src
LICENSE		LICENSE
README.md		README.md

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UART

My implementation of a UART RX/TX module in SystemVerilog.

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My implementation of a UART RX/TX module in SystemVerilog.

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SystemVerilog 100.0%