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TOSHIBA modules updated #483

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527b274
TOSHIBA modules changes
Ivanca21 Oct 7, 2025
ffba325
uart updated to where i left off
Ivanca21 Oct 7, 2025
db2aa8b
urat TX interrupt works
Ivanca21 Oct 8, 2025
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71 changes: 71 additions & 0 deletions targets/arm/mikroe/common/include/flatten_me.h
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Original file line number Diff line number Diff line change
@@ -0,0 +1,71 @@
/****************************************************************************
**
** Copyright (C) MikroElektronika d.o.o.
** Contact: https://www.mikroe.com/contact
**
** Commercial License Usage
**
** Licensees holding valid commercial NECTO compilers AI licenses may use this
** file in accordance with the commercial license agreement provided with the
** Software or, alternatively, in accordance with the terms contained in
** a written agreement between you and The MikroElektronika Company.
** For licensing terms and conditions see
** https://www.mikroe.com/legal/software-license-agreement.
** For further information use the contact form at
** https://www.mikroe.com/contact.
**
**
** GNU Lesser General Public License Usage
**
** Alternatively, this file may be used for
** non-commercial projects under the terms of the GNU Lesser
** General Public License version 3 as published by the Free Software
** Foundation: https://www.gnu.org/licenses/lgpl-3.0.html.
**
** The above copyright notice and this permission notice shall be
** included in all copies or substantial portions of the Software.
**
** THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
** OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
** DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT
** OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
** OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**
****************************************************************************/
/*!
* @file flatten_me.h
* @brief mikroSDK code flattener level selection.
*/

#ifndef __FLATTEN_ME_H__
#define __FLATTEN_ME_H__

#ifdef __cplusplus
extern "C" {
#endif

/**
* @brief Flattening levels.
* @ref FLATTEN_ME_LEVEL_NONE - no code flattening done.
* @ref FLATTEN_ME_LEVEL_LOW - flatten only HAL_LL APIs.
* @ref FLATTEN_ME_LEVEL_MID - flatten only HAL_LL and HAL APIs.
* @ref FLATTEN_ME_LEVEL_HIGH - flatten all layered APIs (HAL_LL, HAL and DRV).
*/
#define FLATTEN_ME_LEVEL_NONE (0)
#define FLATTEN_ME_LEVEL_LOW (1)
#define FLATTEN_ME_LEVEL_MID (2)
#define FLATTEN_ME_LEVEL_HIGH (3)

// Flatten code or not?
#define FLATTEN_ME

// Flatten level selection.
#define FLATTEN_ME_LEVEL FLATTEN_ME_LEVEL_HIGH

#ifdef __cplusplus
}
#endif

#endif // __FLATTEN_ME_H__
76 changes: 76 additions & 0 deletions targets/arm/mikroe/common/include/mcu_definitions/TOSHIBA/TMPM4KNF10AFG/mcu_definitions.h
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Expand Up @@ -92,7 +92,67 @@
//EOF I2C

//UART
/* ====== UART0 ====== */
/* RX */
#define UART0_RX_PC0_FR2
#define UART0_RX_PC1_FR1
#define UART0_RX_PN0_FR2
#define UART0_RX_PN1_FR1
/* TX */
#define UART0_TX_PC1_FR2
#define UART0_TX_PC0_FR1
#define UART0_TX_PN1_FR2
#define UART0_TX_PN0_FR1
/* CTS */
#define UART0_CTS_PD2_FR1
#define UART0_CTS_PN2_FR1
/* RTS */
#define UART0_RTS_PD3_FR1
#define UART0_RTS_PV1_FR1
/* ====== UART1 ====== */
/* RX */
#define UART1_RX_PC4_FR2
#define UART1_RX_PC5_FR1
#define UART1_RX_PU5_FR2
#define UART1_RX_PU6_FR1
/* TX */
#define UART1_TX_PC5_FR2
#define UART1_TX_PC4_FR1
#define UART1_TX_PU6_FR2
#define UART1_TX_PU5_FR1
/* CTS */
#define UART1_CTS_PU4_FR1
/* RTS */
#define UART1_RTS_PU3_FR1
/* ====== UART2 ====== */
/* RX */
#define UART2_RX_PF0_FR2 /* PF0 and PF1 are used for SWD by reset */
#define UART2_RX_PF1_FR1
#define UART2_RX_PU0_FR2
#define UART2_RX_PU1_FR1
/* TX */
#define UART2_TX_PF1_FR2
#define UART2_TX_PF0_FR1
#define UART2_TX_PU1_FR2
#define UART2_TX_PU0_FR1
/* ====== UART3 ====== */
/* RX */
#define UART3_RX_PF3_FR2
#define UART3_RX_PF4_FR1
#define UART3_RX_PF6_FR2
#define UART3_RX_PF7_FR1
/* TX */
#define UART3_TX_PF4_FR2
#define UART3_TX_PF3_FR1
#define UART3_TX_PF7_FR2
#define UART3_TX_PF6_FR1

#define UART_MODULE_COUNT 4

#define UART_MODULE_0 0
#define UART_MODULE_1 1
#define UART_MODULE_2 2
#define UART_MODULE_3 3
//EOF UART

//SPI
Expand Down Expand Up @@ -269,6 +329,22 @@
//EOF GPIO

//IVT_TABLE
#define UART0_RX_NVIC 60 /* INTSC0RX */
#define UART0_TX_NVIC 61 /* INTSC0TX */
#define UART0_ERR_NVIC 62 /* INTSC0ERR */

#define UART1_RX_NVIC 63 /* INTSC1RX */
#define UART1_TX_NVIC 64 /* INTSC1TX */
#define UART1_ERR_NVIC 65 /* INTSC1ERR */

#define UART2_RX_NVIC 66 /* INTSC2RX */
#define UART2_TX_NVIC 67 /* INTSC2TX */
#define UART2_ERR_NVIC 68 /* INTSC2ERR */

#define UART3_RX_NVIC 69 /* INTSC3RX */
#define UART3_TX_NVIC 70 /* INTSC3TX */
#define UART3_ERR_NVIC 71 /* INTSC3ERR */


//EOF IVT_TABLE

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60 changes: 59 additions & 1 deletion targets/arm/mikroe/core/include/hal_ll_core_defines.h
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Expand Up @@ -430,7 +430,7 @@ extern "C"{

#define NVIC_IPR ((NVIC_IPR_Type *) 0xE000E400UL)

#define hal_ll_core_irq(irq_val) (1 << (irq_val & HAL_LL_CORE_IRQ_MASK))
#define hal_ll_core_irq(irq_val) (1 << irq_val)
#define hal_ll_core_pri(irq_pri) (irq_pri << 4)

#define HAL_LL_CORE_IRQ_MASK 0x1F
Expand All @@ -457,6 +457,64 @@ extern "C"{
#define HAL_LL_CORE_NVIC_SCB_SHPR2 (( uint32_t * )0xE000ED1C)
#define HAL_LL_CORE_NVIC_SCB_SHPR3 (( uint32_t * )0xE000ED20)
#endif
#elif defined(toshiba)
#if defined(__cortex_m4__)
typedef enum
{
HAL_LL_IVT_PRIORITY_LEVEL_0 = 0,
HAL_LL_IVT_PRIORITY_LEVEL_1,
HAL_LL_IVT_PRIORITY_LEVEL_2,
HAL_LL_IVT_PRIORITY_LEVEL_3,
HAL_LL_IVT_PRIORITY_LEVEL_4,
HAL_LL_IVT_PRIORITY_LEVEL_5,
HAL_LL_IVT_PRIORITY_LEVEL_6,
HAL_LL_IVT_PRIORITY_LEVEL_7,
HAL_LL_IVT_PRIORITY_LEVEL_8,
HAL_LL_IVT_PRIORITY_LEVEL_9,
HAL_LL_IVT_PRIORITY_LEVEL_10,
HAL_LL_IVT_PRIORITY_LEVEL_11,
HAL_LL_IVT_PRIORITY_LEVEL_12,
HAL_LL_IVT_PRIORITY_LEVEL_13,
HAL_LL_IVT_PRIORITY_LEVEL_14,
HAL_LL_IVT_PRIORITY_LEVEL_15
} hal_ll_core_irq_priority_levels;

/* Eksterni NVIC indeks = IRQn - 16 */
#define hal_ll_core_irq(irq_val) (( irq_val - 16 ))

/* Maske i konstante */
#define HAL_LL_CORE_IRQ_MASK 0x1F
#define HAL_LL_CORE_LOW_NIBBLE 0xFUL
#define HAL_LL_CORE_HIGH_NIBBLE 0xF0UL
#define HAL_LL_CORE_IVT_INT_MEM_MANAGE 4
#define HAL_LL_CORE_IVT_INT_BUS_FAULT 5
#define HAL_LL_CORE_IVT_INT_USAGE_FAULT 6
#define HAL_LL_CORE_IVT_INT_SYS_TICK 15
#define HAL_LL_CORE_IVT_TICKINT_BIT 1
#define HAL_LL_CORE_IVT_MEMFAULTENA_BIT 16
#define HAL_LL_CORE_IVT_BUSFAULTENA_BIT 17
#define HAL_LL_CORE_IVT_USGFAULTENA_BIT 18

/* SCB / SysTick / NVIC (ARM standardna mapa registara) */
#define HAL_LL_CORE_SCB_SHCRS (( uint32_t * )0xE000ED24)
#define HAL_LL_CORE_STK_CTRL (( uint32_t * )0xE000E010)

#define HAL_LL_CORE_NVIC_ISER_0 (( uint32_t * )0xE000E100)
#define HAL_LL_CORE_NVIC_ISER_1 (( uint32_t * )0xE000E104)
#define HAL_LL_CORE_NVIC_ISER_2 (( uint32_t * )0xE000E108)
#define HAL_LL_CORE_NVIC_ISER_3 (( uint32_t * )0xE000E10C)

#define HAL_LL_CORE_NVIC_ICER_0 (( uint32_t * )0xE000E180)
#define HAL_LL_CORE_NVIC_ICER_1 (( uint32_t * )0xE000E184)
#define HAL_LL_CORE_NVIC_ICER_2 (( uint32_t * )0xE000E188)
#define HAL_LL_CORE_NVIC_ICER_3 (( uint32_t * )0xE000E18C)

#define HAL_LL_CORE_NVIC_IPR_0 (( uint32_t * )0xE000E400) /* IPR lutka (8b po IRQ, gornjih 4 bita efektivno) */

#define HAL_LL_CORE_NVIC_SCB_SHPR1 (( uint32_t * )0xE000ED18)
#define HAL_LL_CORE_NVIC_SCB_SHPR2 (( uint32_t * )0xE000ED1C)
#define HAL_LL_CORE_NVIC_SCB_SHPR3 (( uint32_t * )0xE000ED20)
#endif
#endif

#ifdef __cplusplus
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78 changes: 78 additions & 0 deletions targets/arm/mikroe/core/src/toshiba/m4/hal_ll_core_port.c
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Expand Up @@ -48,15 +48,93 @@
void hal_ll_core_port_nvic_enable_irq( uint8_t IRQn )
{
// TODO - Define function behaviour.
/* Sistemski izuzeci */
switch ( IRQn )
{
case HAL_LL_CORE_IVT_INT_MEM_MANAGE:
set_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_MEMFAULTENA_BIT );
break;
case HAL_LL_CORE_IVT_INT_BUS_FAULT:
set_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_BUSFAULTENA_BIT );
break;
case HAL_LL_CORE_IVT_INT_USAGE_FAULT:
set_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_USGFAULTENA_BIT );
break;
case HAL_LL_CORE_IVT_INT_SYS_TICK:
set_reg_bit( HAL_LL_CORE_STK_CTRL, HAL_LL_CORE_IVT_TICKINT_BIT );
break;
default:
break;
}

uint32_t bank = (uint32_t)IRQn >> 5; // div 32
uint32_t bit = (uint32_t)IRQn & 0x1Fu; //mod 32
volatile uint32_t *reg;

if (bank == 0u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ISER_0;
else if (bank == 1u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ISER_1;
else if (bank == 2u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ISER_2;
else reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ISER_3;

*reg = (1u << bit); /* write-1-to-enable */
}

void hal_ll_core_port_nvic_disable_irq( uint8_t IRQn )
{
// TODO - Define function behaviour.
switch ( IRQn )
{
case HAL_LL_CORE_IVT_INT_MEM_MANAGE:
clear_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_MEMFAULTENA_BIT );
break;
case HAL_LL_CORE_IVT_INT_BUS_FAULT:
clear_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_BUSFAULTENA_BIT );
break;
case HAL_LL_CORE_IVT_INT_USAGE_FAULT:
clear_reg_bit( HAL_LL_CORE_SCB_SHCRS, HAL_LL_CORE_IVT_USGFAULTENA_BIT );
break;
case HAL_LL_CORE_IVT_INT_SYS_TICK:
clear_reg_bit( HAL_LL_CORE_STK_CTRL, HAL_LL_CORE_IVT_TICKINT_BIT );
break;
default:
break;
}

uint32_t bank = (uint32_t)IRQn >> 5;
uint32_t bit = (uint32_t)IRQn & 0x1Fu;
volatile uint32_t *reg;

if (bank == 0u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ICER_0;
else if (bank == 1u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ICER_1;
else if (bank == 2u) reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ICER_2;
else reg = (volatile uint32_t*)HAL_LL_CORE_NVIC_ICER_3;

*reg = (1u << bit); /* write-1-to-disable */
}

void hal_ll_core_port_nvic_set_priority_irq( uint8_t IRQn, uint8_t IRQn_priority )
{
// TODO - Define function behaviour.
uintptr_t *reg;
uint8_t tmp_shift;

if ( IRQn > 15 )
{
reg = HAL_LL_CORE_NVIC_IPR_0 + ( ( hal_ll_core_irq( IRQn ) ) >> 2 );
tmp_shift = ( ( ( hal_ll_core_irq( IRQn ) ) % 4 ) << 3 ) + 4;
} else if ( ( IRQn > 3 ) & ( IRQn <= 15 ) ) {
reg = HAL_LL_CORE_NVIC_SCB_SHPR1 + ( IRQn / 4 ) - 1;
tmp_shift = ( ( IRQn % 4 ) << 3 ) + 4;
} else {
return;
}

if ( IRQn_priority & HAL_LL_CORE_LOW_NIBBLE ) {
*reg &= ~( HAL_LL_CORE_LOW_NIBBLE << tmp_shift );
*reg |= ( uint32_t )IRQn_priority << tmp_shift;
} else {
*reg &= ~( HAL_LL_CORE_LOW_NIBBLE << tmp_shift );
*reg |= ( uint32_t )IRQn_priority << ( tmp_shift - 4 );
}
}
// ------------------------------------------------------------------------- END
22 changes: 11 additions & 11 deletions ...include/spi_master/hal_ll_spi_master_pin_map/implementation_1/hal_ll_spi_master_pin_map.h
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Expand Up @@ -101,38 +101,38 @@ static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_sck_map[] = {
/*!< SPI MISO pins. */
static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_miso_map[] = {
#ifdef SPI_MODULE_0
#ifdef SPI0_MISO_PA3_AF1
{GPIO_PA3, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF1},
#ifdef SPI0_MISO_PA2_AF1
{GPIO_PA2, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF1},
#endif
#ifdef SPI0_MISO_PC4_AF3
{GPIO_PC4, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF3},
#ifdef SPI0_MISO_PC3_AF3
{GPIO_PC3, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF3},
#endif
#endif
#ifdef SPI_MODULE_1
#ifdef SPI1_MISO_PG4_AF1
{GPIO_PG4, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), HAL_LL_SPI1_MASTER_GPIO_AF1},
#endif
#ifdef SPI1_MISO_PV1_AF2
{GPIO_PV1, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), HAL_LL_SPI1_MASTER_GPIO_AF2},
#endif
#endif
{HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC}
};

/*!< SPI MOSI pins. */
static const hal_ll_spi_master_pin_map_t hal_ll_spi_master_mosi_map[] = {
#ifdef SPI_MODULE_0
#ifdef SPI0_MOSI_PA2_AF1
{GPIO_PA2, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF1},
#ifdef SPI0_MOSI_PA3_AF1
{GPIO_PA3, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF1},
#endif
#ifdef SPI0_MOSI_PC3_AF3
{GPIO_PC3, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF3},
#ifdef SPI0_MOSI_PC4_AF3
{GPIO_PC4, HAL_LL_SPI0_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_0), HAL_LL_SPI0_MASTER_GPIO_AF3},
#endif
#endif
#ifdef SPI_MODULE_1
#ifdef SPI1_MOSI_PG5_AF1
{GPIO_PG5, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), HAL_LL_SPI1_MASTER_GPIO_AF1},
#endif
#ifdef SPI1_MOSI_PV1_AF2
{GPIO_PV1, HAL_LL_SPI1_MASTER_BASE_ADDR, hal_ll_spi_master_module_num(SPI_MODULE_1), HAL_LL_SPI1_MASTER_GPIO_AF2},
#endif
#endif
{HAL_LL_PIN_NC, HAL_LL_MODULE_ERROR, HAL_LL_PIN_NC, HAL_LL_PIN_NC}
};
Expand Down
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