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Allow allocation and loop to have different positions of device IDs #5323

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Merged
merged 5 commits into from
Oct 7, 2025
Merged

Allow allocation and loop to have different positions of device IDs #5323

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e5818cc
diff order of alloc and loop
Oct 2, 2025
8812fd4
Merge branch 'main' into pm/alloc_order
Priya2698 Oct 4, 2025
d17bc04
do not return reduction IDs in getShardedIterDomain
Priya2698 Oct 7, 2025
aa99629
ignore device dim when verifying vectorized id allocation
Priya2698 Oct 7, 2025
2e4e25b
review
Priya2698 Oct 7, 2025
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2 changes: 1 addition & 1 deletion csrc/device_lower/validation.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -699,7 +699,7 @@ class VectorizeValidator : public OptInDispatch {
size_t last_alloc_dim_pos = 0;
for (size_t i = tv->getMaybeAllocationDomain().size(); i > 0; i--) {
auto r_id = tv->getMaybeAllocationDomain()[i - 1];
if (r_id->isReduction() || r_id->isBroadcast()) {
if (r_id->isReduction() || r_id->isBroadcast() || r_id->isDeviceDim()) {
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@Priya2698 Priya2698 Oct 7, 2025

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DIDx is not reordered to the front in allocation domain and may appear in the innermost position. For e..g. test_matmul.test_linear_reduce_scatter (the copy kernel is pointwise scheduled and codegen-ed).

continue;
}
if ((tv->getMemoryType() == MemoryType::Shared ||
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9 changes: 5 additions & 4 deletions csrc/multidevice/utils.cpp
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Expand Up @@ -228,7 +228,7 @@ IterDomain* getShardedIterDomain(
NVF_THROW("Unexpected parallel type: ", parallel_type);
}();

for (auto&& [index, id] : enumerate(domain)) {
for (IterDomain* id : domain | TensorDomain::kNoReductions) {
if (id->getParallelType() == parallel_type) {
return id;
}
Expand Down Expand Up @@ -266,9 +266,10 @@ std::vector<int64_t> unshardedSizes(
}

const int64_t sharded_axis = getProducingLogicalAxis(tv, sharded_id);
if (sharded_axis == -1) {
continue;
}
NVF_ERROR(
sharded_axis != -1,
"Producing logical axis not found for ",
sharded_id);

auto multiplier = [&]() -> int64_t {
if (parallel_type == ParallelType::Stream) {
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35 changes: 2 additions & 33 deletions csrc/preseg_passes/finalize_multidevice_domains.cpp
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Expand Up @@ -91,39 +91,8 @@ void setLoopAndAllocationDomain(TensorView* tv, bool is_resharding) {
new_allocation_domain.push_back(id);
new_contiguity.push_back(contiguity);
}

std::optional<std::vector<int64_t>> permutation =
ir_utils::computePermutation(new_allocation_domain, tv->getLoopDomain());
NVF_ERROR(
permutation.has_value(),
"Failed to find a valid permutation for reordering ",
tv->getLoopDomain(),
" as ",
new_allocation_domain);
tv->reorder(permutation.value());

if (is_resharding) {
// Resharding expressions have specific requirements on position of
// gathered/scattered dimensions in the allocation domain that is ensured
// by ReorderShardedAxisPass. So we do not move the DIDx to the front in
// this case. For example, in reduce-scatter, the scattered axis is the
// outer-most dimension in communication input and output.
tv->setAllocationDomain(tv->getLoopDomain(), new_contiguity);
return;
}

// Most schedulers require DIDx to be at the front of the loop domain.
auto old2new = reorderParallelizedToFront(tv);
auto new2old = ir_utils::normalizeOld2New(old2new, tv->nDims());
std::vector<std::optional<bool>> reordered_contiguity;
std::transform(
new2old.begin(),
new2old.end(),
std::back_inserter(reordered_contiguity),
[&new_contiguity](int64_t i) -> std::optional<bool> {
return new_contiguity[i];
});
tv->setAllocationDomain(tv->getLoopDomain(), reordered_contiguity);
tv->setAllocationDomain(new_allocation_domain, new_contiguity);
reorderParallelizedToFront(tv);
}

} // namespace
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