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@fuzz6001 fuzz6001 commented Sep 4, 2025

This PR fixes a register mapping error affecting MUL and DIV instructions.

The sixth register in the operand list was incorrectly assigned to R3, which does not match the expected architecture behavior. It has been updated to R4 to ensure correct decoding and operand selection.

@GhidorahRex GhidorahRex self-assigned this Sep 4, 2025
@GhidorahRex GhidorahRex added Type: Bug Something isn't working Feature: Processor/8051 Status: Triage Information is being gathered labels Sep 4, 2025
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Feature: Processor/8051 Status: Triage Information is being gathered Type: Bug Something isn't working
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