Description

This is a Vivado project demonstrating how to get the DDR3 on a Alchitry AU FPGA to store a line of data. It's written in verilog, uses the MIG IP, and lights up on the on board LEDs based on pass/fail of the data storage check.

Motivation

I put this up because it has been surpringly hard to find a simple DDR example project that didnt use a soft processor.

References

• https://alchitry.com/ddr3-memory
• https://numato.com/kb/learning-fpga-verilog-beginners-guide-part-6-ddr-sdram-a7/