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Refactoring riscv64 ISA tests to make use by multiple cores easier
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Jbalkind committed Sep 23, 2023
1 parent e8cb2ec commit f00ed67
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Showing 20 changed files with 434 additions and 297 deletions.
4 changes: 2 additions & 2 deletions piton/verif/diag/master_diaglist
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Expand Up @@ -31,11 +31,11 @@
// ifdef SPARCV9
#endif
#ifdef RISCV64
#include "riscv/rv64/master_diaglist_riscv64"
#include "riscv/rv64/diaglist_riscv64"
// ifdef RISCV64
#endif
#ifdef RISCV32
#include "riscv/rv32/master_diaglist_riscv32"
#include "riscv/rv32/diaglist_riscv32"
// ifdef RISCV32
#endif
</all>
File renamed without changes.
84 changes: 84 additions & 0 deletions piton/verif/diag/riscv/rv64/diaglist_riscv64
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<ariane_tile1 sys=manycore -x_tiles=1 -y_tiles=1 -ariane>
<cmp_default name=default>
// note: these asm tests assume that the RISCV tests have been precompiled with the
// correct environment
<ariane_tile1_asm_tests_p>
<runargs -ariane>
#include "riscv/rv64/rv64ui-p.diaglist"
#include "riscv/rv64/rv64mi-p.diaglist"
#include "riscv/rv64/rv64si-p.diaglist"
#include "riscv/rv64/rv64um-p.diaglist"
</runargs>
</ariane_tile1_asm_tests_p>

// note: these asm tests assume that the RISCV tests have been precompiled with the
// correct environment
<ariane_tile1_asm_tests_v>
<runargs -ariane>
#include "riscv/rv64/rv64ui-v.diaglist"
#include "riscv/rv64/rv64um-v.diaglist"
</runargs>
</ariane_tile1_asm_tests_v>

// note: these asm tests assume that the RISCV tests have been precompiled with the
// correct environment
<ariane_tile1_amo_tests_p>
<runargs -ariane>
#include "riscv/rv64/rv64ua-p.diaglist"
</runargs>
</ariane_tile1_amo_tests_p>

// note: these asm tests assume that the RISCV tests have been precompiled with the
// correct environment
<ariane_tile1_amo_tests_v>
<runargs -ariane>
#include "riscv/rv64/rv64ua-v.diaglist"
</runargs>
</ariane_tile1_amo_tests_v>

// note: these asm tests assume that the RISCV tests have been precompiled with the
// correct environment
<ariane_tile1_fp_tests_p>
<runargs -ariane>
#include "riscv/rv64/rv64uf-p.diaglist"
#include "riscv/rv64/rv64ud-p.diaglist"
</runargs>
</ariane_tile1_fp_tests_p>

// note: these asm tests assume that the RISCV tests have been precompiled with the
// correct environment
<ariane_tile1_fp_tests_v>
<runargs -ariane>
#include "riscv/rv64/rv64uf-v.diaglist"
#include "riscv/rv64/rv64ud-v.diaglist"
</runargs>
</ariane_tile1_fp_tests_v>

// note: these asm tests assume that the RISCV tests have been precompiled with the
// correct environment
<ariane_tile1_benchmarks>
<runargs -ariane>
#include "riscv/rv64/rv64-benchmarks.diaglist"
</runargs>
</ariane_tile1_benchmarks>

<ariane_tile1_simple>
<runargs -x_tiles=1 -y_tiles=1 -ariane -rtl_timeout 1000000>
ariane-hello-world hello_world.c
ariane-accu accu_test.c
ariane-amo-align amo_align.c
</runargs>
</ariane_tile1_simple>

</cmp_default>
</ariane_tile1>

<ariane_tile16 sys=manycore -x_tiles=4 -y_tiles=4 -ariane>
<cmp_default name=default>
<ariane_tile16_simple>
<runargs -x_tiles=4 -y_tiles=4 hello_world.c -ariane -finish_mask=1111111111111111 -rtl_timeout 10000000>
ariane-hello-world-many hello_world_many.c
</runargs>
</ariane_tile16_simple>
</cmp_default>
</ariane_tile16>
295 changes: 0 additions & 295 deletions piton/verif/diag/riscv/rv64/master_diaglist_riscv64

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