Documentation RISC V core based on TL verilog

Table of Contents

• Lab Report
• About RISC V
• Learnings and Observation
• Key Concepts
• Conclusion
• Certificate
• Acknowledgement

LAB reports

Day 1 & 2	Lab report
Day 3 to 5	Lab report

About RISC V

RISC-V is an open standard Instruction Set Architecture (ISA) enabling a new era of processor innovation through open collaboration website: RSIC-V website

Learnings and Observation

1. Tools:

• Makerchip
• Spike simulator
• RISCV GCC TOOLCHAIN

2. Installation:

• Install script Installs Spike simulator and GCC toolchain required to compile RISCV source code in C

3. Usage:

• Compile command:

$ riscv64-unkown-elf-gcc -O<1/fast> -mabi=lp<XLEN> -march=rv<XLEN>i -o <output_program> <input_user_file> [<input_user_file>...]

• Assembly preview command:

$ riscv64-unkown-elf-objdump -d <output_program>

• Run command:

$ spike pk <output_program>

• Debug command:

$ spike -d pk <output_program>

Key Concepts

• RISC V concepts like ISA ABI etc
• TL Verilog concepts
• Pipelining
• Validity
• Hierarchy and Arrays
• Micro architecture of CPU
• Pipelining implementation

Conclusion

Implemented a RISC V core Using TL verilog in 5 days as a part of the Workshop learning key concepts . However the core is bare minimum the workshop helps to understand the underlying concepts clearly.

Certificate

Acknowledgement

• Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd.
• Steve Hoover, Founder, Redwood EDA