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2,325 contributions in the last year
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Contribution activity
March 2025
Created 114 commits in 1 repository
Created a pull request in llvm/llvm-project that received 18 comments
[X86] combineINSERT_SUBVECTOR - fold insert_subvector(base,extract_subvector(broadcast)) -> blend shuffle(base,broadcast)
If the broadcast is already the full vector width, try to prefer a blend over a vector insertion which is usually a lower latency (and sometimes a …
Opened 66 other pull requests in 1 repository
llvm/llvm-project
63
merged
3
open
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[X86] Add test coverage for the concatable sources vpermv3 -> vpermv fold for non-constant shuffle masks
This contribution was made on Mar 28
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[DAG] visitEXTRACT_SUBVECTOR - accumulate SimplifyDemandedVectorElts demanded elts across all EXTRACT_SUBVECTOR uses (REAPPLIED)
This contribution was made on Mar 28
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[DAG] visitEXTRACT_SUBVECTOR - accumulate SimplifyDemandedVectorElts demanded elts across all EXTRACT_SUBVECTOR uses
This contribution was made on Mar 26
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[X86] SimplifyDemandedBitsForTargetNode - add X86ISD::BLENDI handling
This contribution was made on Mar 26
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[X86] combineEXTRACT_SUBVECTOR - extract from a larger subvector insertion
This contribution was made on Mar 25
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[X86] combineConcatVectorOps - add concatenation handling for X86ISD::VSHLD/VSHRD funnel shift nodes
This contribution was made on Mar 25
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[DAG] canCreateUndefOrPoison - add EXTRACT_SUBVECTOR handling
This contribution was made on Mar 24
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[X86] combineConcatVectorOps - always concatenate integer binops with duplicated operands
This contribution was made on Mar 24
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[X86] Allow znver3/4/5 targets to use double-shift instructions by default
This contribution was made on Mar 24
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[X86] combineX86ShufflesRecursively - replace Root node argument with opcode/valuetype/ismaskedshuffle data. NFC.
This contribution was made on Mar 21
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[X86] combineGatherScatter - pull out repeated index sign bits code. NFC.
This contribution was made on Mar 21
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[X86] combineConcatVectorOps - add concatenation handling for consecutive extracts of upper subvectors
This contribution was made on Mar 21
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[X86] combineConcatVectorOps - add concatenation handling for X86ISD::VPERMILPV nodes
This contribution was made on Mar 21
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[CostModel][X86] check all reduction cost kinds using -cost-kind=all
This contribution was made on Mar 19
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[CostModel][X86] merge masked intrinsics costs tests using -cost-kind=all
This contribution was made on Mar 19
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[CostModel][X86] merge fmaxnum/fminnum costs tests using -cost-kind=all
This contribution was made on Mar 18
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[CostModel][X86] merge integer comparison costs tests using -cost-kind=all
This contribution was made on Mar 18
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[CostModel][X86] merge fp comparison costs tests using -cost-kind=all
This contribution was made on Mar 18
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[CostModel][X86] merge integer div/rem costs tests using -cost-kind=all
This contribution was made on Mar 18
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[CostModel][X86] merge truncation costs tests using -cost-kind=all
This contribution was made on Mar 18
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[CostModel][X86] merge funnel shifts costs tests using -cost-kind=all
This contribution was made on Mar 18
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[CostModel][X86] merge select costs tests using -cost-kind=all
This contribution was made on Mar 18
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[CostModel][X86] merge integer multiply costs tests using -cost-kind=all
This contribution was made on Mar 18
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[CostModel][X86] merge integer arithmetic costs tests using -cost-kind=all
This contribution was made on Mar 18
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[CostModel][X86] merge fp arithmetic costs tests using -cost-kind=all
This contribution was made on Mar 18
- Some pull requests not shown.
Reviewed 74 pull requests in 1 repository
llvm/llvm-project
25 pull requests
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[VectorCombine] Shrink loads used in shufflevector rebroadcasts
This contribution was made on Mar 26
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[SLP]Support revectorization of the previously vectorized scalars
This contribution was made on Mar 26
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[SLP]Initial support for (masked)loads + compress and (masked)interleaved
This contribution was made on Mar 26
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[X86] combineINSERT_SUBVECTOR - fold insert_subvector(base,extract_subvector(broadcast)) -> blend shuffle(base,broadcast)
This contribution was made on Mar 26
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[X86] SimplifyDemandedBitsForTargetNode - add X86ISD::BLENDI handling
This contribution was made on Mar 26
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[X86] Use hasSingleElement (NFC)
This contribution was made on Mar 26
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release/20.x: [X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824)
This contribution was made on Mar 25
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[SDAG][tests] add some test cases covering an add-based rotate
This contribution was made on Mar 25
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[X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2
This contribution was made on Mar 25
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[MC] Account for AcquireAtCycle in getReciprocalThroughput
This contribution was made on Mar 24
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[SLP]Fix perfect diamond match with extractelements in scalars
This contribution was made on Mar 24
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[X86]
combinePMULH
- combinemulhu
+srl
This contribution was made on Mar 24 -
[X86][GlobalISel] Support addr matching in SDAG patterns
This contribution was made on Mar 24
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[X86][GlobalISel] Added support for SQRT function
This contribution was made on Mar 24
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[AMDGPU][CodeGenPrepare] Narrow 64 bit math to 32 bit if profitable
This contribution was made on Mar 24
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[NFC][X86] Correct Zen4 Scheduling (Part 1/2: Rename "19h" to "Zen4")
This contribution was made on Mar 21
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[X86][AVX10.2] Remove YMM rounding from VCVTTP.*QS
This contribution was made on Mar 21
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[DAG] Combine (sext (sext_in_reg x)) to (sext_in_reg (any_extend x))
This contribution was made on Mar 21
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[X86][AVX10.2] Remove YMM rounding from VCVT2PS2PHX
This contribution was made on Mar 21
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[X86][AVX10.2] Remove YMM rounding from VMINMAXP[H,S,D]
This contribution was made on Mar 21
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[DAG] SDPatternMatch - add matchers for reassociatable binops
This contribution was made on Mar 21
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[MCA] Extend -instruction-tables option with verbosity levels
This contribution was made on Mar 21
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Revert "[X86][AVX10.2] Support YMM rounding new instructions (#101825)"
This contribution was made on Mar 21
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[DAGCombiner] Attempt to fold 'add' nodes to funnel-shift or rotate
This contribution was made on Mar 21
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[DAG][X86]added shrd in combineor for bzhiq+shlq+or
This contribution was made on Mar 21
- Some pull request reviews not shown.
Created an issue in llvm/llvm-project that received 11 comments
Failure to recognise unnecessary sext for add+cmp
Pulled out #76524 - we fail to recognize that extension is unnecessary and that the trunc is nsw define i8 @src(i16 noundef %x) { entry: %conv = sext
Opened 2 other issues in 1 repository
llvm/llvm-project
2
closed
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[CVP] Failure to recognise trunc nsw from assumptions
This contribution was made on Mar 6
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[VectorCombine] scalarizeLoadExtract - infinite loop if we scalarize a dead extract waiting to be erased
This contribution was made on Mar 1