Wave Transform to generate SSA Exec mask manipulation instrs #789
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| Original file line number | Diff line number | Diff line change |
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@@ -1839,7 +1839,7 @@ void ControlFlowRewriter::rewrite() { | |
| Opcode = AMDGPU::S_CBRANCH_SCC1; | ||
| } else { | ||
| Register CondReg = Info.OrigCondition; | ||
| if (!LMA.isSubsetOfExec(CondReg, *Node->Block, Node->Block->end())) { | ||
| CondReg = LMU.createLaneMaskReg(); | ||
| BuildMI(*Node->Block, Node->Block->end(), {}, TII.get(LMC.AndOpc), | ||
| CondReg) | ||
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@@ -1937,7 +1937,8 @@ void ControlFlowRewriter::rewrite() { | |
| } | ||
| } else { | ||
| CondReg = LaneOrigin.CondReg; | ||
| if (!LMA.isSubsetOfExec(LaneOrigin.CondReg, *LaneOrigin.Node->Block, | ||
| LaneOrigin.Node->Block->getFirstTerminator())) { | ||
| Register Prev = CondReg; | ||
| CondReg = LMU.createLaneMaskReg(); | ||
| BuildMI(*LaneOrigin.Node->Block, | ||
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@@ -2033,28 +2034,34 @@ void ControlFlowRewriter::rewrite() { | |
| CFGNodeInfo &PredInfo = NodeInfo.find(Pred)->second; | ||
| Register PrimaryExec = PredInfo.PrimarySuccessorExec; | ||
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| // Turning off this copy-chain optimization to retain the Accumulator as | ||
| // the PrimaryExec | ||
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| // MachineInstr *PrimaryExecDef; | ||
| // for (;;) { | ||
| // PrimaryExecDef = MRI.getVRegDef(PrimaryExec); | ||
| // if (PrimaryExecDef->getOpcode() != AMDGPU::COPY) | ||
| // break; | ||
| // PrimaryExec = PrimaryExecDef->getOperand(1).getReg(); | ||
| // } | ||
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| // Rejoin = EXEC ^ PrimaryExec | ||
| // | ||
| // Fold immediately if PrimaryExec was obtained via XOR as well. | ||
| Register Rejoin; | ||
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| // Turning off this XOR optimiztion since buildMergeLaneMasks() will not | ||
| // introduce XOR instruction for creating the PrimaryExec | ||
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| // if (PrimaryExecDef->getParent() == Pred->Block && | ||
| // PrimaryExecDef->getOpcode() == LMC.XorOpc && | ||
| // PrimaryExecDef->getOperand(1).isReg() && | ||
| // PrimaryExecDef->getOperand(2).isReg()) { | ||
| // if (PrimaryExecDef->getOperand(1).getReg() == LMC.ExecReg) | ||
| // Rejoin = PrimaryExecDef->getOperand(2).getReg(); | ||
| // else if (PrimaryExecDef->getOperand(2).getReg() == LMC.ExecReg) | ||
| // Rejoin = PrimaryExecDef->getOperand(1).getReg(); | ||
| // } | ||
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| if (!Rejoin) { | ||
| // Try to find a previously generated XOR (or merely masked) value | ||
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@@ -2091,7 +2098,7 @@ void ControlFlowRewriter::rewrite() { | |
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| LLVM_DEBUG(Function.dump()); | ||
| } | ||
| Updater.insertAccumulatorResets(); | ||
| Updater.cleanup(); | ||
| } | ||
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| Original file line number | Diff line number | Diff line change |
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@@ -31,13 +31,14 @@ bool GCNLaneMaskUtils::maybeLaneMask(Register Reg) const { | |
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| /// Determine whether the lane-mask register \p Reg is a wave-wide constant. | ||
| /// If so, the value is stored in \p Val. | ||
| bool GCNLaneMaskUtils::isConstantLaneMask( | ||
| Register Reg, bool &Val, MachineBasicBlock &MBB, | ||
| MachineBasicBlock::iterator MI) const { | ||
| MachineRegisterInfo &MRI = MF.getRegInfo(); | ||
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| for (;;) { | ||
| MI = MRI.getDomVRegDefInBasicBlock(Reg, MBB, MI); | ||
| if (MI == MBB.end()) { | ||
| // This can happen when called from GCNLaneMaskUpdater, where Reg can | ||
| // be a placeholder that has not yet been filled in. | ||
| return false; | ||
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@@ -100,18 +101,17 @@ Register GCNLaneMaskUtils::createLaneMaskReg() const { | |
| /// properly masked, i.e. use PrevReg directly instead of | ||
| /// (PrevReg & ~EXEC), and don't add extra 1-bits to DstReg | ||
| /// beyond (CurReg & EXEC). | ||
| /// \param isPrevZeroReg Indicates that PrevReg is a zero register. | ||
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| void GCNLaneMaskUtils::buildMergeLaneMasks( | ||
| MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, | ||
| Register DstReg, Register PrevReg, Register CurReg, | ||
| GCNLaneMaskAnalysis *LMA, bool accumulating, bool isPrevZeroReg) const { | ||
| const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>(); | ||
| const SIInstrInfo *TII = ST.getInstrInfo(); | ||
| bool PrevVal = false; | ||
| bool PrevConstant = !PrevReg || isPrevZeroReg; | ||
| bool CurVal = false; | ||
| bool CurConstant = isConstantLaneMask(CurReg, CurVal, MBB, I); | ||
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| assert(PrevReg || !accumulating); | ||
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@@ -147,7 +147,7 @@ void GCNLaneMaskUtils::buildMergeLaneMasks(MachineBasicBlock &MBB, | |
| } | ||
| if (!CurConstant) { | ||
| if ((PrevConstant && PrevVal) || | ||
| (LMA && LMA->isSubsetOfExec(CurReg, MBB, I))) { | ||
| CurMaskedReg = CurReg; | ||
| } else { | ||
| CurMaskedReg = createLaneMaskReg(); | ||
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@@ -188,22 +188,26 @@ void GCNLaneMaskUtils::buildMergeLaneMasks(MachineBasicBlock &MBB, | |
| /// (Reg & EXEC) == Reg when used in \p UseBlock. | ||
| bool GCNLaneMaskAnalysis::isSubsetOfExec(Register Reg, | ||
| MachineBasicBlock &UseBlock, | ||
| MachineBasicBlock::iterator I, | ||
| unsigned RemainingDepth) { | ||
| MachineRegisterInfo &MRI = LMU.function()->getRegInfo(); | ||
| MachineBasicBlock::iterator DefInstr = UseBlock.end(); | ||
| const AMDGPU::LaneMaskConstants &LMC = LMU.getLaneMaskConsts(); | ||
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| for (;;) { | ||
| if (!Register::isVirtualRegister(Reg)) { | ||
| if (Reg == LMC.ExecReg && | ||
| (DefInstr == UseBlock.end() || DefInstr->getParent() == &UseBlock)) | ||
| return true; | ||
| return false; | ||
| } | ||
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| DefInstr = MRI.getDomVRegDefInBasicBlock(Reg, UseBlock, I); | ||
| if (DefInstr == UseBlock.end()) | ||
| return false; | ||
| if (DefInstr->getOpcode() == AMDGPU::COPY) { | ||
| Reg = DefInstr->getOperand(1).getReg(); | ||
| I = DefInstr; | ||
| continue; | ||
| } | ||
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@@ -242,7 +246,7 @@ bool GCNLaneMaskAnalysis::isSubsetOfExec(Register Reg, | |
| if ((LikeOr || IsAnd || IsAndN2) && | ||
| (DefInstr->getOperand(1).isReg() && DefInstr->getOperand(2).isReg())) { | ||
| bool FirstIsSubset = isSubsetOfExec(DefInstr->getOperand(1).getReg(), | ||
| UseBlock, DefInstr, RemainingDepth); | ||
| if (!FirstIsSubset && (LikeOr || IsAndN2)) | ||
| return SubsetOfExec.try_emplace(Reg, false).first->second; | ||
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@@ -252,7 +256,7 @@ bool GCNLaneMaskAnalysis::isSubsetOfExec(Register Reg, | |
| } | ||
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| bool SecondIsSubset = isSubsetOfExec(DefInstr->getOperand(2).getReg(), | ||
| UseBlock, DefInstr, RemainingDepth); | ||
| if (!SecondIsSubset) | ||
| return SubsetOfExec.try_emplace(Reg, false).first->second; | ||
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@@ -268,14 +272,14 @@ void GCNLaneMaskUpdater::init(Register Reg) { | |
| Processed = false; | ||
| Blocks.clear(); | ||
| // SSAUpdater.Initialize(LMU.getLaneMaskConsts().LaneMaskRC); | ||
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| Accumulator = {}; | ||
| } | ||
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| /// Optional cleanup, may remove stray instructions. | ||
| void GCNLaneMaskUpdater::cleanup() { | ||
| Processed = false; | ||
| Blocks.clear(); | ||
| Accumulator = {}; | ||
| MachineRegisterInfo &MRI = LMU.function()->getRegInfo(); | ||
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| if (ZeroReg && MRI.use_empty(ZeroReg)) { | ||
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@@ -330,7 +334,7 @@ void GCNLaneMaskUpdater::addAvailable(MachineBasicBlock &Block, | |
| Register GCNLaneMaskUpdater::getValueInMiddleOfBlock(MachineBasicBlock &Block) { | ||
| if (!Processed) | ||
| process(); | ||
| return Accumulator; | ||
| } | ||
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| /// Return the value at the end of the given block, i.e. after any change that | ||
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@@ -342,7 +346,7 @@ Register GCNLaneMaskUpdater::getValueInMiddleOfBlock(MachineBasicBlock &Block) { | |
| Register GCNLaneMaskUpdater::getValueAtEndOfBlock(MachineBasicBlock &Block) { | ||
| if (!Processed) | ||
| process(); | ||
| return Accumulator; | ||
| } | ||
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| /// Return the value in \p Block after the value merge (if any). | ||
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@@ -352,15 +356,15 @@ Register GCNLaneMaskUpdater::getValueAfterMerge(MachineBasicBlock &Block) { | |
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| auto BlockIt = findBlockInfo(Block); | ||
| if (BlockIt != Blocks.end()) { | ||
| if (BlockIt->Value) | ||
| return Accumulator; | ||
| if (BlockIt->Flags & ResetInMiddle) | ||
| return ZeroReg; | ||
| } | ||
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| // We didn't merge anything in the block, but the block may still be | ||
| // ResetAtEnd, in which case we need the pre-reset value. | ||
| return Accumulator; | ||
| } | ||
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| /// Determine whether \p MI defines and/or uses SCC. | ||
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@@ -422,22 +426,22 @@ void GCNLaneMaskUpdater::process() { | |
| .addImm(0); | ||
| } | ||
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| if (!Accumulator) { | ||
| Accumulator = LMU.createLaneMaskReg(); | ||
| BuildMI(Entry, Entry.getFirstTerminator(), {}, | ||
| TII->get(LMU.getLaneMaskConsts().MovOpc), Accumulator) | ||
| .addImm(0); | ||
| } | ||
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| // Reset accumulator. | ||
| for (BlockInfo &Info : Blocks) { | ||
| assert(Accumulating || !Info.Flags); | ||
| assert(Info.Flags || Info.Value); | ||
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| if (!Info.Value || (Info.Flags & ResetAtEnd)) | ||
| AccumulatorResetBlocks[Info.Block].insert(Accumulator); | ||
| } | ||
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| // Once the SSA updater is ready, we can fill in all merge code, relying | ||
| // on the SSA updater to insert required PHIs. | ||
| for (BlockInfo &Info : Blocks) { | ||
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@@ -448,11 +452,8 @@ void GCNLaneMaskUpdater::process() { | |
| Register Previous; | ||
| if (Info.Block != &LMU.function()->front() && | ||
| !(Info.Flags & ResetInMiddle)) { | ||
| Previous = Accumulator; | ||
| if (!Accumulating) { | ||
| MachineInstr *PrevInstr = MRI.getVRegDef(Previous); | ||
| if (PrevInstr && PrevInstr->getOpcode() == AMDGPU::IMPLICIT_DEF) { | ||
| PotentiallyDead.insert(PrevInstr); | ||
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@@ -466,18 +467,19 @@ void GCNLaneMaskUpdater::process() { | |
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| // Insert merge logic. | ||
| MachineBasicBlock::iterator insertPt = getSaluInsertionAtEnd(*Info.Block); | ||
| LMU.buildMergeLaneMasks(*Info.Block, insertPt, {}, Accumulator, Previous, | ||
| Info.Value, LMA, Accumulating, Previous == ZeroReg); | ||
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| // Switching off this optimization, since Accumulator will always have a use | ||
| // if (Info.Flags & ResetAtEnd) { | ||
| // MachineInstr *mergeInstr = MRI.getVRegDef(Info.Merged); | ||
| // if (mergeInstr->getOpcode() == AMDGPU::COPY && | ||
| // mergeInstr->getOperand(1).getReg().isVirtual()) { | ||
| // assert(MRI.use_empty(Info.Merged)); | ||
| // Info.Merged = mergeInstr->getOperand(1).getReg(); | ||
| // mergeInstr->eraseFromParent(); | ||
| // } | ||
| // } | ||
| } | ||
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| Processed = true; | ||
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@@ -489,3 +491,22 @@ GCNLaneMaskUpdater::findBlockInfo(MachineBasicBlock &Block) { | |
| return llvm::find_if( | ||
| Blocks, [&](const auto &Entry) { return Entry.Block == &Block; }); | ||
| } | ||
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| void GCNLaneMaskUpdater::insertAccumulatorResets() { | ||
| const SIInstrInfo *TII = | ||
| LMU.function()->getSubtarget<GCNSubtarget>().getInstrInfo(); | ||
| for (auto &Entry : AccumulatorResetBlocks) { | ||
| MachineBasicBlock *B = Entry.first; | ||
| DenseSet<Register> &Accumulators = Entry.second; | ||
| for (Register ACC : Accumulators) { | ||
| // Get first branch instruction. | ||
| MachineBasicBlock::iterator I = B->getFirstTerminator(); | ||
| while (I != B->end() && !I->isBranch()) | ||
| I++; | ||
| if (I == B->end()) | ||
| I--; | ||
| BuildMI(*B, I, {}, TII->get(LMU.getLaneMaskConsts().MovOpc), ACC) | ||
| .addImm(0); | ||
| } | ||
|
There was a problem hiding this comment. Can't you insert all resets one after another once you find the right place rather than searching for right insertion place for every accumulator to reset? Seems bit expensive! |
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| } | ||
| } | ||
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The comment seems bit misleading, as the last instruction while searching backward implies the very first definition in the MBB. I think you can separate the two lines : the last instruction encountered in the MBB & you search in the backward manner from I.