Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Updated to Vivado 2018.3 #1

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

Updated to Vivado 2018.3 #1

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
Zynq Ten-Gigabit Example
========================

This repository contains an example project for two ZC706 boards communicating over a 10-Gigabit network, using optical transcievers in the SFP+ cages on the boards.
This repository contains an example project for two ZC706 boards communicating over a 10-Gigabit network, using optical transceivers in the SFP+ cages on the boards.

The project structure is as follows:

Expand Down
8 changes: 4 additions & 4 deletions master_hw/block_design.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2015.2
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
Expand Down Expand Up @@ -155,7 +155,7 @@ proc create_root_design { parentCell } {
set txp [ create_bd_port -dir O txp ]

# Create instance: axi_10g_ethernet_0, and set properties
set axi_10g_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_10g_ethernet:3.0 axi_10g_ethernet_0 ]
set axi_10g_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_10g_ethernet:3.1 axi_10g_ethernet_0 ]
set_property -dict [ list CONFIG.SupportLevel {1} ] $axi_10g_ethernet_0

# Create instance: axi_dma_0, and set properties
Expand All @@ -170,11 +170,11 @@ proc create_root_design { parentCell } {
set_property -dict [ list CONFIG.NUM_MI {1} CONFIG.NUM_SI {3} ] $axi_interconnect_1

# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_0 ]
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
set_property -dict [ list CONFIG.FIFO_DEPTH {2048} CONFIG.FIFO_MODE {2} ] $axis_data_fifo_0

# Create instance: axis_data_fifo_1, and set properties
set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_1 ]
set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
set_property -dict [ list CONFIG.FIFO_DEPTH {2048} CONFIG.FIFO_MODE {2} ] $axis_data_fifo_1

# Create instance: const_sig_detect_high, and set properties
Expand Down
4 changes: 2 additions & 2 deletions master_hw/project.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ set_property "xelab.unifast" "" $obj

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7z045ffg900-2 -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
create_run -name synth_1 -part xc7z045ffg900-2 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
Expand All @@ -110,7 +110,7 @@ current_run -synthesis [get_runs synth_1]

# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part xc7z045ffg900-2 -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
create_run -name impl_1 -part xc7z045ffg900-2 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2015" [get_runs impl_1]
Expand Down
8 changes: 4 additions & 4 deletions slave_hw/block_design.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2015.2
set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
Expand Down Expand Up @@ -155,19 +155,19 @@ proc create_root_design { parentCell } {
set txp [ create_bd_port -dir O txp ]

# Create instance: axi_10g_ethernet_0, and set properties
set axi_10g_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_10g_ethernet:3.0 axi_10g_ethernet_0 ]
set axi_10g_ethernet_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_10g_ethernet:3.1 axi_10g_ethernet_0 ]
set_property -dict [ list CONFIG.SupportLevel {1} ] $axi_10g_ethernet_0

# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list CONFIG.NUM_MI {1} ] $axi_interconnect_0

# Create instance: axis_data_fifo_0, and set properties
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_0 ]
set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
set_property -dict [ list CONFIG.FIFO_MODE {2} ] $axis_data_fifo_0

# Create instance: axis_data_fifo_1, and set properties
set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_1 ]
set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
set_property -dict [ list CONFIG.FIFO_MODE {2} ] $axis_data_fifo_1

# Create instance: proc_sys_reset_0, and set properties
Expand Down
4 changes: 2 additions & 2 deletions slave_hw/project.tcl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ set_property "xelab.unifast" "" $obj

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
create_run -name synth_1 -part xc7z045ffg900-2 -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
create_run -name synth_1 -part xc7z045ffg900-2 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
} else {
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
Expand All @@ -110,7 +110,7 @@ current_run -synthesis [get_runs synth_1]

# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
create_run -name impl_1 -part xc7z045ffg900-2 -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
create_run -name impl_1 -part xc7z045ffg900-2 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
} else {
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property flow "Vivado Implementation 2015" [get_runs impl_1]
Expand Down