update framework with edge coupled SiN PCM #8
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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The design is on Layer 1/5. Could you move to 4/0? 
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Also we may want to put the origin in the middle, like ANT requests. |
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also, please remove the FloorPlan box (the one that covers the entire chip), since I will use that to check for overlaps with other Floorplans before placing the cell. |
Use the Floorplan layer when merging, to ensure designs don't overlap with each other. Should work for any PCM shapes.
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I remap the layers to 4/0 in the EBeam_merge.py script. |
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