Silicon Photonics : Layout draft submission [archanas] #101
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this layout had opt_in label error as i had mentioned in discussion/live Q&A
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Welcome, new contributor! Thank you for uploading your design. If you have not already checked it, please run the SiEPIC Functional Verification in KLayout, using the menu SiEPIC-Verification-Functional Layout Check (V). You may continue making updates to your design, or even contributing additonal designs (using a separate file name), until the tape-out deadline. |
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Thank you for your pull request! 👋 |
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I see still these errors |
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hi, |
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Measured to be 127.05, check your editor setting |
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Silicon Photonics : Layout draft submission [archanas]
eDX username - archana.arch03