Skip to content

fix: correct PTE flags for LoongArch64 and correct TLB flush mask for aarch64 #2

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
Mivik merged 3 commits into from
Jun 16, 2025
Merged

fix: correct PTE flags for LoongArch64 and correct TLB flush mask for aarch64 #2

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
cc5796c
fix: correct page table entry flags for LoongArch64
Aqua-2001 Jun 8, 2025
61b110f
fix: correct TLB invalidation address calculation for aarch64
Aqua-2001 Jun 9, 2025
811caf8
fix: correct TLB invalidate mask for aarch64
Aqua-2001 Jun 10, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 3 additions & 3 deletions page_table_entry/src/arch/loongarch64.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -97,7 +97,7 @@ impl From<MappingFlags> for PTEFlags {
ret |= Self::NR;
}
if f.contains(MappingFlags::WRITE) {
ret |= Self::W;
ret |= Self::W | Self::D;
}
if !f.contains(MappingFlags::EXECUTE) {
ret |= Self::NX;
Expand Down Expand Up @@ -134,7 +134,7 @@ impl LA64PTE {

impl GenericPTE for LA64PTE {
fn new_page(paddr: PhysAddr, flags: MappingFlags, is_huge: bool) -> Self {
let mut flags = PTEFlags::from(flags) | PTEFlags::D;
let mut flags = PTEFlags::from(flags);
if is_huge {
flags |= PTEFlags::GH;
}
Expand All @@ -153,7 +153,7 @@ impl GenericPTE for LA64PTE {
self.0 = (self.0 & !Self::PHYS_ADDR_MASK) | (paddr.as_usize() as u64 & Self::PHYS_ADDR_MASK)
}
fn set_flags(&mut self, flags: MappingFlags, is_huge: bool) {
let mut flags = PTEFlags::from(flags) | PTEFlags::D;
let mut flags = PTEFlags::from(flags);
if is_huge {
flags |= PTEFlags::GH;
}
Expand Down
3 changes: 2 additions & 1 deletion page_table_multiarch/src/arch/aarch64.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,8 @@ impl PagingMetaData for A64PagingMetaData {
unsafe {
if let Some(vaddr) = vaddr {
// TLB Invalidate by VA, All ASID, EL1, Inner Shareable
asm!("tlbi vaae1is, {}; dsb sy; isb", in(reg) vaddr.as_usize())
// va[55:12] => reg[43:0]
asm!("tlbi vaae1is, {}; dsb sy; isb", in(reg) ((vaddr.as_usize() >> 12) & 0xFFF_FFFF_FFFF))
} else {
// TLB Invalidate by VMID, All at stage 1, EL1
asm!("tlbi vmalle1; dsb sy; isb")
Expand Down