fix: add VDSO data modules for aarch64, loongarch64, riscv64 archs

src/aarch64/config.rs

@@ -4,4 +4,4 @@ pub const VVAR_PAGES: usize = 5;
 pub enum ClockMode {
     None,
     Cntvct,
-}
+}

src/aarch64/mod.rs

@@ -1 +1,2 @@
-
+pub mod config;
+pub mod vdso_data;

src/aarch64/vdso_data.rs

@@ -1,3 +1,13 @@
+use axplat::time::{
+    NANOS_PER_SEC, current_ticks, monotonic_time_nanos, nanos_to_ticks, wall_time_nanos,
+};
+
+use super::config::ClockMode;
+use crate::{
+    update::{clocks_calc_mult_shift, update_vdso_clock},
+    vdso::VdsoClock,
+};
+
 #[repr(C)]
 #[repr(align(4096))]
 pub struct VdsoData {
@@ -37,28 +47,28 @@ impl VdsoData {
         let mult_shift = clocks_calc_mult_shift(ticks_per_sec, NANOS_PER_SEC, 10);
         let cycle_now = current_ticks();
 
-        data.clock_page0.write_seqcount_begin();
-        data.clock_page0.clock_mode = ClockMode::Cntvct as i32;
-        data.clock_page0.mask = u64::MAX;
+        self.clock_page0.write_seqcount_begin();
+        self.clock_page0.clock_mode = ClockMode::Cntvct as i32;
+        self.clock_page0.mask = u64::MAX;
         update_vdso_clock(
-            &mut data.clock_page0,
+            &mut self.clock_page0,
             cycle_now,
             wall_ns,
             mono_ns,
             mult_shift,
         );
-        data.clock_page0.write_seqcount_end();
+        self.clock_page0.write_seqcount_end();
 
-        data.clock_page1.write_seqcount_begin();
-        data.clock_page1.clock_mode = ClockMode::Cntvct as i32;
-        data.clock_page1.mask = u64::MAX;
+        self.clock_page1.write_seqcount_begin();
+        self.clock_page1.clock_mode = ClockMode::Cntvct as i32;
+        self.clock_page1.mask = u64::MAX;
         update_vdso_clock(
-            &mut data.clock_page1,
+            &mut self.clock_page1,
             cycle_now,
             wall_ns,
             mono_ns,
             mult_shift,
         );
-        data.clock_page1.write_seqcount_end();
+        self.clock_page1.write_seqcount_end();
     }
-}
+}

src/embed.rs

@@ -23,7 +23,7 @@ cfg_if::cfg_if! {
     if #[cfg(target_arch = "x86_64")] {
         global_asm!(include_vdso!("x86_64"));
     } else if #[cfg(target_arch = "riscv64")] {
-        global_asm!(include_vdso!("riscv"));
+        global_asm!(include_vdso!("riscv64"));
     } else if #[cfg(target_arch = "aarch64")]{
         global_asm!(include_vdso!("aarch64"));
     } else if #[cfg(any(target_arch = "loongarch64"))] {

src/loongarch64/config.rs

@@ -4,4 +4,4 @@ pub const VVAR_PAGES: usize = 44;
 pub enum ClockMode {
     None,
     Csr,
-}
+}

src/loongarch64/mod.rs

@@ -1 +1,2 @@
-
+pub mod config;
+pub mod vdso_data;

src/loongarch64/vdso_data.rs

@@ -1,3 +1,12 @@
+use axplat::time::{
+    NANOS_PER_SEC, current_ticks, monotonic_time_nanos, nanos_to_ticks, wall_time_nanos,
+};
+
+use crate::{
+    update::{clocks_calc_mult_shift, update_vdso_clock},
+    vdso::VdsoClock,
+};
+
 #[repr(C)]
 #[repr(align(4096))]
 #[derive(Default)]
@@ -28,10 +37,10 @@ impl VdsoData {
         let ticks_per_sec = nanos_to_ticks(NANOS_PER_SEC);
         let mult_shift = clocks_calc_mult_shift(ticks_per_sec, NANOS_PER_SEC, 10);
 
-        for clk in &mut data.clocks {
+        for clk in &mut self.clocks {
             clk.write_seqcount_begin();
             update_vdso_clock(clk, cycle_now, wall_ns, mono_ns, mult_shift);
             clk.write_seqcount_end();
         }
     }
-}
+}

src/riscv64/config.rs

@@ -4,4 +4,4 @@ pub const VVAR_PAGES: usize = 2;
 pub enum ClockMode {
     None,
     Csr,
-}
+}

src/riscv64/mod.rs

@@ -1 +1,2 @@
-
+pub mod config;
+pub mod vdso_data;

src/riscv64/vdso_data.rs

@@ -1,3 +1,12 @@
+use axplat::time::{
+    NANOS_PER_SEC, current_ticks, monotonic_time_nanos, nanos_to_ticks, wall_time_nanos,
+};
+
+use crate::{
+    update::{clocks_calc_mult_shift, update_vdso_clock},
+    vdso::VdsoClock,
+};
+
 #[repr(C)]
 #[repr(align(4096))]
 #[derive(Default)]
@@ -26,10 +35,10 @@ impl VdsoData {
         let ticks_per_sec = nanos_to_ticks(NANOS_PER_SEC);
         let mult_shift = clocks_calc_mult_shift(ticks_per_sec, NANOS_PER_SEC, 10);
 
-        for clk in &mut data.clocks {
+        for clk in &mut self.clocks {
             clk.write_seqcount_begin();
             update_vdso_clock(clk, cycle_now, wall_ns, mono_ns, mult_shift);
             clk.write_seqcount_end();
         }
     }
-}
+}