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Synthesys-Lab / assassyn Public

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Simplify top generator.#422

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were wants to merge 4 commits intoSynthesys-Lab:masterSynthesys-Lab/assassyn:masterfrom

were:simptop-251102were/assassyn:simptop-251102Copy head branch name to clipboard

Conversation Commits4 (4)Checks Files changed

Open

Simplify top generator.#422
were wants to merge 4 commits intoSynthesys-Lab:masterfrom
were:simptop-251102

Commits

Commits on Nov 2, 2025

[verilog] Retire dumper get_pred helper.
were
committed
verilog: derive external wiring from metadata
were
committed
[verilog] Refresh backend helpers and tests\n[python/assassyn/codegen/verilog/top.py] Introduce TopHarnessBuilder helpers and reuse them during top-level emission.\n[python/assassyn/codegen/verilog…
were
committed

Commits on Nov 18, 2025

ok... rename them to and_/or_
were
committed

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