WIFI-14438: Fix LAN port issue in Edgecore EAP105

Signed-off-by: Tanya Singh <[email protected]>
Telecominfraproject · Feb 25, 2025 · ba73333 · ba73333
1 parent 24dbba4
commit ba73333
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Showing 2 changed files with 22 additions and 2 deletions.
diff --git a/feeds/qca/ipq53xx/base-files/etc/board.d/03_gpio_switches b/feeds/qca/ipq53xx/base-files/etc/board.d/03_gpio_switches
@@ -0,0 +1,18 @@
+#!/bin/sh
+
+. /lib/functions/uci-defaults.sh
+
+board_config_update
+
+board=$(board_name)
+
+case $board in
+edgecore,eap105)
+        ucidef_add_gpio_switch "eth1_phy_reset_down" "eth1_PHY_reset_down" "481" "0"
+        ucidef_add_gpio_switch "eth1_phy_reset_up" "eth1_PHY_reset_up" "481" "1"
+        ;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/feeds/qca/ipq53xx/dts/ipq5332-edgecore-eap105.dts b/feeds/qca/ipq53xx/dts/ipq5332-edgecore-eap105.dts
@@ -37,7 +37,7 @@
 		mdio:mdio@90000 {
 			pinctrl-0 = <&mdio1_pins>;
 			pinctrl-names = "default";
-			phy-reset-gpio = <&tlmm 24 GPIO_ACTIVE_LOW &tlmm 22 GPIO_ACTIVE_LOW>;
+			phy-reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
 			phyaddr_fixup = <0xC90F018>;
 			uniphyaddr_fixup = <0xC90F014>;
 			mdio_clk_fixup; /* MDIO clock sequence fix up flag */
@@ -46,6 +46,8 @@
 			phy0: ethernet-phy@0 {
 				reg = <2>;
 				compatible = "ethernet-phy-id001c.c916";
+				realtek,clkout-disable;
+				realtek,aldps-enable;
 			};
 
 			phy1: ethernet-phy@1 {
@@ -97,7 +99,7 @@
 			compatible = "qcom,nss-dp";
 			qcom,id = <1>;
 			reg = <0x3a500000 0x4000>;
-			qcom,mactype = <1>;
+			qcom,mactype = <0>;
 			local-mac-address = [000000000000];
 			mdio-bus = <&mdio>;
 			qcom,phy-mdio-addr = <2>;