- We are working on creating some hardware cores using Chisel, an HDL (not HLS) written inside of Scala
- Chisel is a well tested and was used to create the RISC-V Instruction Set Architecture
- Additionally we are working on setting up the pipeline to use free and open source tools for everything from design to synthesis
The Chiselers
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dynamicfifo
dynamicfifo Public templateForked from rocksavagetech/dynamicfifo
A highly configurable FIFO or FIFO controller with dynamic status flags.
Verilog
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- registermap Public
The-Chiselers/registermap’s past year of commit activity - addrdecode Public
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